1/* 2 * Copyright (c) 2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55void 56MemDelay::init() 57{ 58 if (!slavePort.isConnected() || !masterPort.isConnected()) 59 fatal("Memory delay is not connected on both sides.\n"); 60} 61 62 |
63Port & 64MemDelay::getPort(const std::string &if_name, PortID idx) |
65{ 66 if (if_name == "master") { 67 return masterPort; |
68 } else if (if_name == "slave") { |
69 return slavePort; 70 } else { |
71 return MemObject::getPort(if_name, idx); |
72 } 73} 74 75bool 76MemDelay::trySatisfyFunctional(PacketPtr pkt) 77{ 78 return slavePort.trySatisfyFunctional(pkt) || 79 masterPort.trySatisfyFunctional(pkt); --- 129 unchanged lines hidden --- |