1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#include "mem/mem_delay.hh"
41
42#include "params/MemDelay.hh"
43#include "params/SimpleMemDelay.hh"
44
45MemDelay::MemDelay(const MemDelayParams *p)
| 1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#include "mem/mem_delay.hh"
41
42#include "params/MemDelay.hh"
43#include "params/SimpleMemDelay.hh"
44
45MemDelay::MemDelay(const MemDelayParams *p)
|
46 : MemObject(p),
| 46 : ClockedObject(p),
|
47 masterPort(name() + "-master", *this),
48 slavePort(name() + "-slave", *this),
49 reqQueue(*this, masterPort),
50 respQueue(*this, slavePort),
51 snoopRespQueue(*this, masterPort)
52{
53}
54
55void
56MemDelay::init()
57{
58 if (!slavePort.isConnected() || !masterPort.isConnected())
59 fatal("Memory delay is not connected on both sides.\n");
60}
61
62
63Port &
64MemDelay::getPort(const std::string &if_name, PortID idx)
65{
66 if (if_name == "master") {
67 return masterPort;
68 } else if (if_name == "slave") {
69 return slavePort;
70 } else {
| 47 masterPort(name() + "-master", *this),
48 slavePort(name() + "-slave", *this),
49 reqQueue(*this, masterPort),
50 respQueue(*this, slavePort),
51 snoopRespQueue(*this, masterPort)
52{
53}
54
55void
56MemDelay::init()
57{
58 if (!slavePort.isConnected() || !masterPort.isConnected())
59 fatal("Memory delay is not connected on both sides.\n");
60}
61
62
63Port &
64MemDelay::getPort(const std::string &if_name, PortID idx)
65{
66 if (if_name == "master") {
67 return masterPort;
68 } else if (if_name == "slave") {
69 return slavePort;
70 } else {
|
71 return MemObject::getPort(if_name, idx);
| 71 return ClockedObject::getPort(if_name, idx);
|
72 }
73}
74
75bool
76MemDelay::trySatisfyFunctional(PacketPtr pkt)
77{
78 return slavePort.trySatisfyFunctional(pkt) ||
79 masterPort.trySatisfyFunctional(pkt);
80}
81
82MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
83 : QueuedMasterPort(_name, &_parent,
84 _parent.reqQueue, _parent.snoopRespQueue),
85 parent(_parent)
86{
87}
88
89bool
90MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
91{
92 const Tick when = curTick() + parent.delayResp(pkt);
93
94 parent.slavePort.schedTimingResp(pkt, when);
95
96 return true;
97}
98
99void
100MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt)
101{
102 if (parent.trySatisfyFunctional(pkt)) {
103 pkt->makeResponse();
104 } else {
105 parent.slavePort.sendFunctionalSnoop(pkt);
106 }
107}
108
109Tick
110MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt)
111{
112 const Tick delay = parent.delaySnoopResp(pkt);
113
114 return delay + parent.slavePort.sendAtomicSnoop(pkt);
115}
116
117void
118MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt)
119{
120 parent.slavePort.sendTimingSnoopReq(pkt);
121}
122
123
124MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent)
125 : QueuedSlavePort(_name, &_parent, _parent.respQueue),
126 parent(_parent)
127{
128}
129
130Tick
131MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
132{
133 const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
134
135 return delay + parent.masterPort.sendAtomic(pkt);
136}
137
138bool
139MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
140{
141 const Tick when = curTick() + parent.delayReq(pkt);
142
143 parent.masterPort.schedTimingReq(pkt, when);
144
145 return true;
146}
147
148void
149MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
150{
151 if (parent.trySatisfyFunctional(pkt)) {
152 pkt->makeResponse();
153 } else {
154 parent.masterPort.sendFunctional(pkt);
155 }
156}
157
158bool
159MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt)
160{
161 const Tick when = curTick() + parent.delaySnoopResp(pkt);
162
163 parent.masterPort.schedTimingSnoopResp(pkt, when);
164
165 return true;
166}
167
168
169
170SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams *p)
171 : MemDelay(p),
172 readReqDelay(p->read_req),
173 readRespDelay(p->read_resp),
174 writeReqDelay(p->write_req),
175 writeRespDelay(p->write_resp)
176{
177}
178
179Tick
180SimpleMemDelay::delayReq(PacketPtr pkt)
181{
182 if (pkt->isRead()) {
183 return readReqDelay;
184 } else if (pkt->isWrite()) {
185 return writeReqDelay;
186 } else {
187 return 0;
188 }
189}
190
191Tick
192SimpleMemDelay::delayResp(PacketPtr pkt)
193{
194 if (pkt->isRead()) {
195 return readRespDelay;
196 } else if (pkt->isWrite()) {
197 return writeRespDelay;
198 } else {
199 return 0;
200 }
201}
202
203
204SimpleMemDelay *
205SimpleMemDelayParams::create()
206{
207 return new SimpleMemDelay(this);
208}
| 72 }
73}
74
75bool
76MemDelay::trySatisfyFunctional(PacketPtr pkt)
77{
78 return slavePort.trySatisfyFunctional(pkt) ||
79 masterPort.trySatisfyFunctional(pkt);
80}
81
82MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
83 : QueuedMasterPort(_name, &_parent,
84 _parent.reqQueue, _parent.snoopRespQueue),
85 parent(_parent)
86{
87}
88
89bool
90MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
91{
92 const Tick when = curTick() + parent.delayResp(pkt);
93
94 parent.slavePort.schedTimingResp(pkt, when);
95
96 return true;
97}
98
99void
100MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt)
101{
102 if (parent.trySatisfyFunctional(pkt)) {
103 pkt->makeResponse();
104 } else {
105 parent.slavePort.sendFunctionalSnoop(pkt);
106 }
107}
108
109Tick
110MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt)
111{
112 const Tick delay = parent.delaySnoopResp(pkt);
113
114 return delay + parent.slavePort.sendAtomicSnoop(pkt);
115}
116
117void
118MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt)
119{
120 parent.slavePort.sendTimingSnoopReq(pkt);
121}
122
123
124MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent)
125 : QueuedSlavePort(_name, &_parent, _parent.respQueue),
126 parent(_parent)
127{
128}
129
130Tick
131MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
132{
133 const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);
134
135 return delay + parent.masterPort.sendAtomic(pkt);
136}
137
138bool
139MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
140{
141 const Tick when = curTick() + parent.delayReq(pkt);
142
143 parent.masterPort.schedTimingReq(pkt, when);
144
145 return true;
146}
147
148void
149MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
150{
151 if (parent.trySatisfyFunctional(pkt)) {
152 pkt->makeResponse();
153 } else {
154 parent.masterPort.sendFunctional(pkt);
155 }
156}
157
158bool
159MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt)
160{
161 const Tick when = curTick() + parent.delaySnoopResp(pkt);
162
163 parent.masterPort.schedTimingSnoopResp(pkt, when);
164
165 return true;
166}
167
168
169
170SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams *p)
171 : MemDelay(p),
172 readReqDelay(p->read_req),
173 readRespDelay(p->read_resp),
174 writeReqDelay(p->write_req),
175 writeRespDelay(p->write_resp)
176{
177}
178
179Tick
180SimpleMemDelay::delayReq(PacketPtr pkt)
181{
182 if (pkt->isRead()) {
183 return readReqDelay;
184 } else if (pkt->isWrite()) {
185 return writeReqDelay;
186 } else {
187 return 0;
188 }
189}
190
191Tick
192SimpleMemDelay::delayResp(PacketPtr pkt)
193{
194 if (pkt->isRead()) {
195 return readRespDelay;
196 } else if (pkt->isWrite()) {
197 return writeRespDelay;
198 } else {
199 return 0;
200 }
201}
202
203
204SimpleMemDelay *
205SimpleMemDelayParams::create()
206{
207 return new SimpleMemDelay(this);
208}
|