mem_checker_monitor.cc (13784:1941dc118243) mem_checker_monitor.cc (13892:0182a0601f66)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#include <memory>
45
46#include "base/logging.hh"
47#include "base/output.hh"
48#include "base/trace.hh"
49#include "debug/MemCheckerMonitor.hh"
50
51MemCheckerMonitor::MemCheckerMonitor(Params* params)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#include <memory>
45
46#include "base/logging.hh"
47#include "base/output.hh"
48#include "base/trace.hh"
49#include "debug/MemCheckerMonitor.hh"
50
51MemCheckerMonitor::MemCheckerMonitor(Params* params)
52 : MemObject(params),
52 : SimObject(params),
53 masterPort(name() + "-master", *this),
54 slavePort(name() + "-slave", *this),
55 warnOnly(params->warn_only),
56 memchecker(params->memchecker)
57{}
58
59MemCheckerMonitor::~MemCheckerMonitor()
60{}

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76Port &
77MemCheckerMonitor::getPort(const std::string &if_name, PortID idx)
78{
79 if (if_name == "master" || if_name == "mem_side") {
80 return masterPort;
81 } else if (if_name == "slave" || if_name == "cpu_side") {
82 return slavePort;
83 } else {
53 masterPort(name() + "-master", *this),
54 slavePort(name() + "-slave", *this),
55 warnOnly(params->warn_only),
56 memchecker(params->memchecker)
57{}
58
59MemCheckerMonitor::~MemCheckerMonitor()
60{}

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76Port &
77MemCheckerMonitor::getPort(const std::string &if_name, PortID idx)
78{
79 if (if_name == "master" || if_name == "mem_side") {
80 return masterPort;
81 } else if (if_name == "slave" || if_name == "cpu_side") {
82 return slavePort;
83 } else {
84 return MemObject::getPort(if_name, idx);
84 return SimObject::getPort(if_name, idx);
85 }
86}
87
88void
89MemCheckerMonitor::recvFunctional(PacketPtr pkt)
90{
91 Addr addr = pkt->getAddr();
92 unsigned size = pkt->getSize();

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86}
87
88void
89MemCheckerMonitor::recvFunctional(PacketPtr pkt)
90{
91 Addr addr = pkt->getAddr();
92 unsigned size = pkt->getSize();

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