mem_checker_monitor.cc (10713:eddb533708cb) mem_checker_monitor.cc (11284:b3926db25371)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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151 // or even deleted when sendTiming() is called.
152 //
153 // For reads we are only interested in real reads, and not prefetches, as
154 // it is not guaranteed that the prefetch returns any useful data.
155 bool is_read = pkt->isRead() && !pkt->req->isPrefetch();
156 bool is_write = pkt->isWrite();
157 unsigned size = pkt->getSize();
158 Addr addr = pkt->getAddr();
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 142 unchanged lines hidden (view full) ---

151 // or even deleted when sendTiming() is called.
152 //
153 // For reads we are only interested in real reads, and not prefetches, as
154 // it is not guaranteed that the prefetch returns any useful data.
155 bool is_read = pkt->isRead() && !pkt->req->isPrefetch();
156 bool is_write = pkt->isWrite();
157 unsigned size = pkt->getSize();
158 Addr addr = pkt->getAddr();
159 bool expects_response = pkt->needsResponse() && !pkt->memInhibitAsserted();
159 bool expects_response = pkt->needsResponse() && !pkt->cacheResponding();
160 std::unique_ptr<uint8_t> pkt_data;
161 MemCheckerMonitorSenderState* state = NULL;
162
163 if (expects_response && is_write) {
164 // On receipt of a request, only need to allocate pkt_data if this is a
165 // write. For reads, we have no data yet, so it doesn't make sense to
166 // allocate.
167 pkt_data.reset(new uint8_t[size]);
168 memcpy(pkt_data.get(), pkt->getConstPtr<uint8_t*>(), size);
169 }
170
171 // If a cache miss is served by a cache, a monitor near the memory
172 // would see a request which needs a response, but this response
160 std::unique_ptr<uint8_t> pkt_data;
161 MemCheckerMonitorSenderState* state = NULL;
162
163 if (expects_response && is_write) {
164 // On receipt of a request, only need to allocate pkt_data if this is a
165 // write. For reads, we have no data yet, so it doesn't make sense to
166 // allocate.
167 pkt_data.reset(new uint8_t[size]);
168 memcpy(pkt_data.get(), pkt->getConstPtr<uint8_t*>(), size);
169 }
170
171 // If a cache miss is served by a cache, a monitor near the memory
172 // would see a request which needs a response, but this response
173 // would be inhibited and not come back from the memory. Therefore
173 // would not come back from the memory. Therefore
174 // we additionally have to check the inhibit flag.
175 if (expects_response && (is_read || is_write)) {
176 state = new MemCheckerMonitorSenderState(0);
177 pkt->pushSenderState(state);
178 }
179
174 // we additionally have to check the inhibit flag.
175 if (expects_response && (is_read || is_write)) {
176 state = new MemCheckerMonitorSenderState(0);
177 pkt->pushSenderState(state);
178 }
179
180 // Attempt to send the packet (always succeeds for inhibited
181 // packets)
180 // Attempt to send the packet
182 bool successful = masterPort.sendTimingReq(pkt);
183
184 // If not successful, restore the sender state
185 if (!successful && expects_response && (is_read || is_write)) {
186 delete pkt->popSenderState();
187 }
188
189 if (successful && expects_response) {

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222 "size = %d\n",
223 serial, addr, size);
224 } else {
225 DPRINTF(MemCheckerMonitor,
226 "Forwarded non read/write request: addr = %#llx\n", addr);
227 }
228 } else if (successful) {
229 DPRINTF(MemCheckerMonitor,
181 bool successful = masterPort.sendTimingReq(pkt);
182
183 // If not successful, restore the sender state
184 if (!successful && expects_response && (is_read || is_write)) {
185 delete pkt->popSenderState();
186 }
187
188 if (successful && expects_response) {

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221 "size = %d\n",
222 serial, addr, size);
223 } else {
224 DPRINTF(MemCheckerMonitor,
225 "Forwarded non read/write request: addr = %#llx\n", addr);
226 }
227 } else if (successful) {
228 DPRINTF(MemCheckerMonitor,
230 "Forwarded inhibited request: addr = %#llx\n", addr);
229 "Forwarded request marked for cache response: addr = %#llx\n",
230 addr);
231 }
232
233 return successful;
234}
235
236bool
237MemCheckerMonitor::recvTimingResp(PacketPtr pkt)
238{

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232
233 return successful;
234}
235
236bool
237MemCheckerMonitor::recvTimingResp(PacketPtr pkt)
238{

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