1/* |
2 * Copyright (c) 2011,2013 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 34 unchanged lines hidden (view full) --- 45 * @file 46 * Port object definitions. 47 */ 48 49#include "base/chunk_generator.hh" 50#include "cpu/base.hh" 51#include "cpu/thread_context.hh" 52#include "mem/fs_translating_port_proxy.hh" |
53#include "sim/system.hh" |
54 55using namespace TheISA; 56 57FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc) |
58 : PortProxy(tc->getCpuPtr()->getDataPort(), 59 tc->getSystemPtr()->cacheLineSize()), _tc(tc) |
60{ 61} 62 |
63FSTranslatingPortProxy::FSTranslatingPortProxy(MasterPort &port, 64 unsigned int cacheLineSize) 65 : PortProxy(port, cacheLineSize), _tc(NULL) |
66{ 67} 68 69FSTranslatingPortProxy::~FSTranslatingPortProxy() 70{ 71} 72 73void --- 92 unchanged lines hidden --- |