1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * Port object definitions.
47 */
48
49#include "mem/fs_translating_port_proxy.hh"
50
51#include "arch/vtophys.hh"
52#include "base/chunk_generator.hh"
53#include "cpu/base.hh"
54#include "cpu/thread_context.hh"
55#include "sim/system.hh"
56
57using namespace TheISA;
58
59FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc)
60 : PortProxy(tc->getCpuPtr()->getDataPort(),
61 tc->getSystemPtr()->cacheLineSize()), _tc(tc)
62{
63}
64
65FSTranslatingPortProxy::FSTranslatingPortProxy(MasterPort &port,
66 unsigned int cacheLineSize)
67 : PortProxy(port, cacheLineSize), _tc(NULL)
68{
69}
70
71FSTranslatingPortProxy::~FSTranslatingPortProxy()
72{
73}
74
75void
76FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) const
77{
78 Addr paddr;
79 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
80 gen.next())
81 {
82 if (_tc)
83 paddr = TheISA::vtophys(_tc,gen.addr());
84 else
85 paddr = TheISA::vtophys(gen.addr());
86
| 1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Andreas Hansson
42 */
43
44/**
45 * @file
46 * Port object definitions.
47 */
48
49#include "mem/fs_translating_port_proxy.hh"
50
51#include "arch/vtophys.hh"
52#include "base/chunk_generator.hh"
53#include "cpu/base.hh"
54#include "cpu/thread_context.hh"
55#include "sim/system.hh"
56
57using namespace TheISA;
58
59FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc)
60 : PortProxy(tc->getCpuPtr()->getDataPort(),
61 tc->getSystemPtr()->cacheLineSize()), _tc(tc)
62{
63}
64
65FSTranslatingPortProxy::FSTranslatingPortProxy(MasterPort &port,
66 unsigned int cacheLineSize)
67 : PortProxy(port, cacheLineSize), _tc(NULL)
68{
69}
70
71FSTranslatingPortProxy::~FSTranslatingPortProxy()
72{
73}
74
75void
76FSTranslatingPortProxy::readBlob(Addr addr, uint8_t *p, int size) const
77{
78 Addr paddr;
79 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
80 gen.next())
81 {
82 if (_tc)
83 paddr = TheISA::vtophys(_tc,gen.addr());
84 else
85 paddr = TheISA::vtophys(gen.addr());
86
|
87 PortProxy::readBlob(paddr, p, gen.size());
| 87 PortProxy::readBlobPhys(paddr, 0, p, gen.size());
|
88 p += gen.size();
89 }
90}
91
92void
93FSTranslatingPortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
94{
95 Addr paddr;
96 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
97 gen.next())
98 {
99 if (_tc)
100 paddr = TheISA::vtophys(_tc,gen.addr());
101 else
102 paddr = TheISA::vtophys(gen.addr());
103
| 88 p += gen.size();
89 }
90}
91
92void
93FSTranslatingPortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
94{
95 Addr paddr;
96 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
97 gen.next())
98 {
99 if (_tc)
100 paddr = TheISA::vtophys(_tc,gen.addr());
101 else
102 paddr = TheISA::vtophys(gen.addr());
103
|
104 PortProxy::writeBlob(paddr, p, gen.size());
| 104 PortProxy::writeBlobPhys(paddr, 0, p, gen.size());
|
105 p += gen.size();
106 }
107}
108
109void
110FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) const
111{
112 Addr paddr;
113 for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done();
114 gen.next())
115 {
116 if (_tc)
117 paddr = TheISA::vtophys(_tc,gen.addr());
118 else
119 paddr = TheISA::vtophys(gen.addr());
120
| 105 p += gen.size();
106 }
107}
108
109void
110FSTranslatingPortProxy::memsetBlob(Addr address, uint8_t v, int size) const
111{
112 Addr paddr;
113 for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done();
114 gen.next())
115 {
116 if (_tc)
117 paddr = TheISA::vtophys(_tc,gen.addr());
118 else
119 paddr = TheISA::vtophys(gen.addr());
120
|
121 PortProxy::memsetBlob(paddr, v, gen.size());
| 121 PortProxy::memsetBlobPhys(paddr, 0, v, gen.size());
|
122 }
123}
124
125void
126CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
127{
128 uint8_t *dst = (uint8_t *)dest;
129 tc->getVirtProxy().readBlob(src, dst, cplen);
130}
131
132void
133CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t cplen)
134{
135 uint8_t *src = (uint8_t *)source;
136 tc->getVirtProxy().writeBlob(dest, src, cplen);
137}
138
139void
140CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
141{
142 char *start = dst;
143 FSTranslatingPortProxy &vp = tc->getVirtProxy();
144
145 bool foundNull = false;
146 while ((dst - start + 1) < maxlen && !foundNull) {
147 vp.readBlob(vaddr++, (uint8_t*)dst, 1);
148 if (*dst == '\0')
149 foundNull = true;
150 dst++;
151 }
152
153 if (!foundNull)
154 *dst = '\0';
155}
156
157void
158CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr)
159{
160 FSTranslatingPortProxy &vp = tc->getVirtProxy();
161 for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();
162 gen.next())
163 {
164 vp.writeBlob(gen.addr(), (uint8_t*)src, gen.size());
165 src += gen.size();
166 }
167}
| 122 }
123}
124
125void
126CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
127{
128 uint8_t *dst = (uint8_t *)dest;
129 tc->getVirtProxy().readBlob(src, dst, cplen);
130}
131
132void
133CopyIn(ThreadContext *tc, Addr dest, const void *source, size_t cplen)
134{
135 uint8_t *src = (uint8_t *)source;
136 tc->getVirtProxy().writeBlob(dest, src, cplen);
137}
138
139void
140CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
141{
142 char *start = dst;
143 FSTranslatingPortProxy &vp = tc->getVirtProxy();
144
145 bool foundNull = false;
146 while ((dst - start + 1) < maxlen && !foundNull) {
147 vp.readBlob(vaddr++, (uint8_t*)dst, 1);
148 if (*dst == '\0')
149 foundNull = true;
150 dst++;
151 }
152
153 if (!foundNull)
154 *dst = '\0';
155}
156
157void
158CopyStringIn(ThreadContext *tc, const char *src, Addr vaddr)
159{
160 FSTranslatingPortProxy &vp = tc->getVirtProxy();
161 for (ChunkGenerator gen(vaddr, strlen(src), TheISA::PageBytes); !gen.done();
162 gen.next())
163 {
164 vp.writeBlob(gen.addr(), (uint8_t*)src, gen.size());
165 src += gen.size();
166 }
167}
|