| dramsim2.hh (12084:5a3769ff3d55) | dramsim2.hh (13784:1941dc118243) |
|---|---|
| 1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 177 unchanged lines hidden (view full) --- 186 * @param id Channel id of the responder 187 * @param addr Address of the request 188 * @param cycle Internal cycle count of DRAMSim2 189 */ 190 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle); 191 192 DrainState drain() override; 193 | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 177 unchanged lines hidden (view full) --- 186 * @param id Channel id of the responder 187 * @param addr Address of the request 188 * @param cycle Internal cycle count of DRAMSim2 189 */ 190 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle); 191 192 DrainState drain() override; 193 |
| 194 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 195 PortID idx = InvalidPortID) override; | 194 Port &getPort(const std::string &if_name, 195 PortID idx=InvalidPortID) override; |
| 196 197 void init() override; 198 void startup() override; 199 200 protected: 201 202 Tick recvAtomic(PacketPtr pkt); 203 void recvFunctional(PacketPtr pkt); 204 bool recvTimingReq(PacketPtr pkt); 205 void recvRespRetry(); 206 207}; 208 209#endif // __MEM_DRAMSIM2_HH__ | 196 197 void init() override; 198 void startup() override; 199 200 protected: 201 202 Tick recvAtomic(PacketPtr pkt); 203 void recvFunctional(PacketPtr pkt); 204 bool recvTimingReq(PacketPtr pkt); 205 void recvRespRetry(); 206 207}; 208 209#endif // __MEM_DRAMSIM2_HH__ |