dramsim2.hh (10913:38dbdeea7f1f) dramsim2.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40/**
41 * @file
42 * DRAMSim2
43 */
44#ifndef __MEM_DRAMSIM2_HH__
45#define __MEM_DRAMSIM2_HH__
46
47#include <queue>
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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40/**
41 * @file
42 * DRAMSim2
43 */
44#ifndef __MEM_DRAMSIM2_HH__
45#define __MEM_DRAMSIM2_HH__
46
47#include <queue>
48#include <unordered_map>
48
49
49#include "base/hashmap.hh"
50#include "mem/abstract_mem.hh"
51#include "mem/dramsim2_wrapper.hh"
52#include "mem/qport.hh"
53#include "params/DRAMSim2.hh"
54
55class DRAMSim2 : public AbstractMemory
56{
57 private:

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109 Tick startTick;
110
111 /**
112 * Keep track of what packets are outstanding per
113 * address, and do so separately for reads and writes. This is
114 * done so that we can return the right packet on completion from
115 * DRAMSim.
116 */
50#include "mem/abstract_mem.hh"
51#include "mem/dramsim2_wrapper.hh"
52#include "mem/qport.hh"
53#include "params/DRAMSim2.hh"
54
55class DRAMSim2 : public AbstractMemory
56{
57 private:

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109 Tick startTick;
110
111 /**
112 * Keep track of what packets are outstanding per
113 * address, and do so separately for reads and writes. This is
114 * done so that we can return the right packet on completion from
115 * DRAMSim.
116 */
117 m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads;
118 m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites;
117 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
118 std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;
119
120 /**
121 * Count the number of outstanding transactions so that we can
122 * block any further requests until there is space in DRAMSim2 and
123 * the sending queue we need to buffer the response packets.
124 */
125 unsigned int nbrOutstandingReads;
126 unsigned int nbrOutstandingWrites;

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184 * Write completion callback.
185 *
186 * @param id Channel id of the responder
187 * @param addr Address of the request
188 * @param cycle Internal cycle count of DRAMSim2
189 */
190 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
191
119
120 /**
121 * Count the number of outstanding transactions so that we can
122 * block any further requests until there is space in DRAMSim2 and
123 * the sending queue we need to buffer the response packets.
124 */
125 unsigned int nbrOutstandingReads;
126 unsigned int nbrOutstandingWrites;

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184 * Write completion callback.
185 *
186 * @param id Channel id of the responder
187 * @param addr Address of the request
188 * @param cycle Internal cycle count of DRAMSim2
189 */
190 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);
191
192 DrainState drain() M5_ATTR_OVERRIDE;
192 DrainState drain() override;
193
194 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
195 PortID idx = InvalidPortID);
196
197 virtual void init();
198 virtual void startup();
199
200 protected:
201
202 Tick recvAtomic(PacketPtr pkt);
203 void recvFunctional(PacketPtr pkt);
204 bool recvTimingReq(PacketPtr pkt);
205 void recvRespRetry();
206
207};
208
209#endif // __MEM_DRAMSIM2_HH__
193
194 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
195 PortID idx = InvalidPortID);
196
197 virtual void init();
198 virtual void startup();
199
200 protected:
201
202 Tick recvAtomic(PacketPtr pkt);
203 void recvFunctional(PacketPtr pkt);
204 bool recvTimingReq(PacketPtr pkt);
205 void recvRespRetry();
206
207};
208
209#endif // __MEM_DRAMSIM2_HH__