dramsim2.hh (10713:eddb533708cb) | dramsim2.hh (10913:38dbdeea7f1f) |
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1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 118 unchanged lines hidden (view full) --- 127 128 /** 129 * Queue to hold response packets until we can send them 130 * back. This is needed as DRAMSim2 unconditionally passes 131 * responses back without any flow control. 132 */ 133 std::deque<PacketPtr> responseQueue; 134 | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 118 unchanged lines hidden (view full) --- 127 128 /** 129 * Queue to hold response packets until we can send them 130 * back. This is needed as DRAMSim2 unconditionally passes 131 * responses back without any flow control. 132 */ 133 std::deque<PacketPtr> responseQueue; 134 |
135 /** 136 * If we need to drain, keep the drain manager around until we're 137 * done here. 138 */ 139 DrainManager *drainManager; 140 | |
141 unsigned int nbrOutstanding() const; 142 143 /** 144 * When a packet is ready, use the "access()" method in 145 * AbstractMemory to actually create the response packet, and send 146 * it back to the outside world requestor. 147 * 148 * @param pkt The packet from the outside world --- 41 unchanged lines hidden (view full) --- 190 * Write completion callback. 191 * 192 * @param id Channel id of the responder 193 * @param addr Address of the request 194 * @param cycle Internal cycle count of DRAMSim2 195 */ 196 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle); 197 | 135 unsigned int nbrOutstanding() const; 136 137 /** 138 * When a packet is ready, use the "access()" method in 139 * AbstractMemory to actually create the response packet, and send 140 * it back to the outside world requestor. 141 * 142 * @param pkt The packet from the outside world --- 41 unchanged lines hidden (view full) --- 184 * Write completion callback. 185 * 186 * @param id Channel id of the responder 187 * @param addr Address of the request 188 * @param cycle Internal cycle count of DRAMSim2 189 */ 190 void writeComplete(unsigned id, uint64_t addr, uint64_t cycle); 191 |
198 unsigned int drain(DrainManager* dm); | 192 DrainState drain() M5_ATTR_OVERRIDE; |
199 200 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 201 PortID idx = InvalidPortID); 202 203 virtual void init(); 204 virtual void startup(); 205 206 protected: 207 208 Tick recvAtomic(PacketPtr pkt); 209 void recvFunctional(PacketPtr pkt); 210 bool recvTimingReq(PacketPtr pkt); 211 void recvRespRetry(); 212 213}; 214 215#endif // __MEM_DRAMSIM2_HH__ | 193 194 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 195 PortID idx = InvalidPortID); 196 197 virtual void init(); 198 virtual void startup(); 199 200 protected: 201 202 Tick recvAtomic(PacketPtr pkt); 203 void recvFunctional(PacketPtr pkt); 204 bool recvTimingReq(PacketPtr pkt); 205 void recvRespRetry(); 206 207}; 208 209#endif // __MEM_DRAMSIM2_HH__ |