dramsim2.cc (11192:4c28abcf8249) dramsim2.cc (11284:b3926db25371)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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150}
151
152Tick
153DRAMSim2::recvAtomic(PacketPtr pkt)
154{
155 access(pkt);
156
157 // 50 ns is just an arbitrary value at this point
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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150}
151
152Tick
153DRAMSim2::recvAtomic(PacketPtr pkt)
154{
155 access(pkt);
156
157 // 50 ns is just an arbitrary value at this point
158 return pkt->memInhibitAsserted() ? 0 : 50000;
158 return pkt->cacheResponding() ? 0 : 50000;
159}
160
161void
162DRAMSim2::recvFunctional(PacketPtr pkt)
163{
164 pkt->pushLabel(name());
165
166 functionalAccess(pkt);
167
168 // potentially update the packets in our response queue as well
169 for (auto i = responseQueue.begin(); i != responseQueue.end(); ++i)
170 pkt->checkFunctional(*i);
171
172 pkt->popLabel();
173}
174
175bool
176DRAMSim2::recvTimingReq(PacketPtr pkt)
177{
159}
160
161void
162DRAMSim2::recvFunctional(PacketPtr pkt)
163{
164 pkt->pushLabel(name());
165
166 functionalAccess(pkt);
167
168 // potentially update the packets in our response queue as well
169 for (auto i = responseQueue.begin(); i != responseQueue.end(); ++i)
170 pkt->checkFunctional(*i);
171
172 pkt->popLabel();
173}
174
175bool
176DRAMSim2::recvTimingReq(PacketPtr pkt)
177{
178 // sink inhibited packets without further action
179 if (pkt->memInhibitAsserted()) {
178 // if a cache is responding, sink the packet without further action
179 if (pkt->cacheResponding()) {
180 pendingDelete.reset(pkt);
181 return true;
182 }
183
184 // we should not get a new request after committing to retry the
185 // current one, but unfortunately the CPU violates this rule, so
186 // simply ignore it for now
187 if (retryReq)

--- 210 unchanged lines hidden --- 		180 pendingDelete.reset(pkt);
181 return true;
182 }
183
184 // we should not get a new request after committing to retry the
185 // current one, but unfortunately the CPU violates this rule, so
186 // simply ignore it for now
187 if (retryReq)

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