dramsim2.cc (10910:32f3d1c454ec) dramsim2.cc (10913:38dbdeea7f1f)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47
48DRAMSim2::DRAMSim2(const Params* p) :
49 AbstractMemory(p),
50 port(name() + ".port", *this),
51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
53 retryReq(false), retryResp(false), startTick(0),
54 nbrOutstandingReads(0), nbrOutstandingWrites(0),
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47
48DRAMSim2::DRAMSim2(const Params* p) :
49 AbstractMemory(p),
50 port(name() + ".port", *this),
51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
53 retryReq(false), retryResp(false), startTick(0),
54 nbrOutstandingReads(0), nbrOutstandingWrites(0),
55 drainManager(NULL),
56 sendResponseEvent(this), tickEvent(this)
57{
58 DPRINTF(DRAMSim2,
59 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
60 wrapper.clockPeriod(), wrapper.queueSize());
61
62 DRAMSim::TransactionCompleteCB* read_cb =
63 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(

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113
114 DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n",
115 nbrOutstandingReads, nbrOutstandingWrites,
116 responseQueue.size());
117
118 if (!responseQueue.empty() && !sendResponseEvent.scheduled())
119 schedule(sendResponseEvent, curTick());
120
55 sendResponseEvent(this), tickEvent(this)
56{
57 DPRINTF(DRAMSim2,
58 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
59 wrapper.clockPeriod(), wrapper.queueSize());
60
61 DRAMSim::TransactionCompleteCB* read_cb =
62 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(

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112
113 DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n",
114 nbrOutstandingReads, nbrOutstandingWrites,
115 responseQueue.size());
116
117 if (!responseQueue.empty() && !sendResponseEvent.scheduled())
118 schedule(sendResponseEvent, curTick());
119
121 // check if we were asked to drain and if we are now done
122 if (drainManager && nbrOutstanding() == 0) {
123 drainManager->signalDrainDone();
124 drainManager = NULL;
125 }
120 if (nbrOutstanding() == 0)
121 signalDrainDone();
126 } else {
127 retryResp = true;
128
129 DPRINTF(DRAMSim2, "Waiting for response retry\n");
130
131 assert(!sendResponseEvent.scheduled());
132 }
133}

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334 // what is outstanding
335 p->second.pop();
336 if (p->second.empty())
337 outstandingWrites.erase(p);
338
339 assert(nbrOutstandingWrites != 0);
340 --nbrOutstandingWrites;
341
122 } else {
123 retryResp = true;
124
125 DPRINTF(DRAMSim2, "Waiting for response retry\n");
126
127 assert(!sendResponseEvent.scheduled());
128 }
129}

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330 // what is outstanding
331 p->second.pop();
332 if (p->second.empty())
333 outstandingWrites.erase(p);
334
335 assert(nbrOutstandingWrites != 0);
336 --nbrOutstandingWrites;
337
342 // check if we were asked to drain and if we are now done
343 if (drainManager && nbrOutstanding() == 0) {
344 drainManager->signalDrainDone();
345 drainManager = NULL;
346 }
338 if (nbrOutstanding() == 0)
339 signalDrainDone();
347}
348
349BaseSlavePort&
350DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
351{
352 if (if_name != "port") {
353 return MemObject::getSlavePort(if_name, idx);
354 } else {
355 return port;
356 }
357}
358
359unsigned int
340}
341
342BaseSlavePort&
343DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
344{
345 if (if_name != "port") {
346 return MemObject::getSlavePort(if_name, idx);
347 } else {
348 return port;
349 }
350}
351
352unsigned int
360DRAMSim2::drain(DrainManager* dm)
353DRAMSim2::drain()
361{
362 // check our outstanding reads and writes and if any they need to
363 // drain
354{
355 // check our outstanding reads and writes and if any they need to
356 // drain
364 if (nbrOutstanding() != 0) {
365 setDrainState(DrainState::Draining);
366 drainManager = dm;
367 return 1;
368 } else {
369 setDrainState(DrainState::Drained);
370 return 0;
371 }
357 return nbrOutstanding() != 0 ? DrainState::Draining : DrainState::Drained;
372}
373
374DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
375 DRAMSim2& _memory)
376 : SlavePort(_name, &_memory), memory(_memory)
377{ }
378
379AddrRangeList

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359
360DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
361 DRAMSim2& _memory)
362 : SlavePort(_name, &_memory), memory(_memory)
363{ }
364
365AddrRangeList

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