| dramsim2.cc (10713:eddb533708cb) | dramsim2.cc (10721:3e6a3eaac71b) |
|---|---|
| 1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 254 unchanged lines hidden (view full) --- 263 // do the actual memory access which also turns the packet into a 264 // response 265 access(pkt); 266 267 // turn packet around to go back to requester if response expected 268 if (needsResponse) { 269 // access already turned the packet into a response 270 assert(pkt->isResponse()); | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 254 unchanged lines hidden (view full) --- 263 // do the actual memory access which also turns the packet into a 264 // response 265 access(pkt); 266 267 // turn packet around to go back to requester if response expected 268 if (needsResponse) { 269 // access already turned the packet into a response 270 assert(pkt->isResponse()); |
| 271 272 // @todo someone should pay for this | 271 // Here we pay for xbar additional delay and to process the payload 272 // of the packet. 273 Tick time = curTick() + pkt->headerDelay + pkt->payloadDelay; 274 // Reset the timings of the packet |
| 273 pkt->headerDelay = pkt->payloadDelay = 0; 274 275 DPRINTF(DRAMSim2, "Queuing response for address %lld\n", 276 pkt->getAddr()); 277 278 // queue it to be sent back 279 responseQueue.push_back(pkt); 280 281 // if we are not already waiting for a retry, or are scheduled 282 // to send a response, schedule an event 283 if (!retryResp && !sendResponseEvent.scheduled()) | 275 pkt->headerDelay = pkt->payloadDelay = 0; 276 277 DPRINTF(DRAMSim2, "Queuing response for address %lld\n", 278 pkt->getAddr()); 279 280 // queue it to be sent back 281 responseQueue.push_back(pkt); 282 283 // if we are not already waiting for a retry, or are scheduled 284 // to send a response, schedule an event 285 if (!retryResp && !sendResponseEvent.scheduled()) |
| 284 schedule(sendResponseEvent, curTick()); | 286 schedule(sendResponseEvent, time); |
| 285 } else { 286 // @todo the packet is going to be deleted, and the DRAMPacket 287 // is still having a pointer to it 288 pendingDelete.push_back(pkt); 289 } 290} 291 292void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle) --- 122 unchanged lines hidden --- | 287 } else { 288 // @todo the packet is going to be deleted, and the DRAMPacket 289 // is still having a pointer to it 290 pendingDelete.push_back(pkt); 291 } 292} 293 294void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle) --- 122 unchanged lines hidden --- |