dramsim2.cc (10694:1a6785e37d81) dramsim2.cc (10713:eddb533708cb)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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142DRAMSim2::tick()
143{
144 wrapper.tick();
145
146 // is the connected port waiting for a retry, if so check the
147 // state and send a retry if conditions have changed
148 if (retryReq && nbrOutstanding() < wrapper.queueSize()) {
149 retryReq = false;
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 133 unchanged lines hidden (view full) ---

142DRAMSim2::tick()
143{
144 wrapper.tick();
145
146 // is the connected port waiting for a retry, if so check the
147 // state and send a retry if conditions have changed
148 if (retryReq && nbrOutstanding() < wrapper.queueSize()) {
149 retryReq = false;
150 port.sendRetry();
150 port.sendRetryReq();
151 }
152
153 schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
154}
155
156Tick
157DRAMSim2::recvAtomic(PacketPtr pkt)
158{

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239 return true;
240 } else {
241 retryReq = true;
242 return false;
243 }
244}
245
246void
151 }
152
153 schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
154}
155
156Tick
157DRAMSim2::recvAtomic(PacketPtr pkt)
158{

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239 return true;
240 } else {
241 retryReq = true;
242 return false;
243 }
244}
245
246void
247DRAMSim2::recvRetry()
247DRAMSim2::recvRespRetry()
248{
249 DPRINTF(DRAMSim2, "Retrying\n");
250
251 assert(retryResp);
252 retryResp = false;
253 sendResponse();
254}
255

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397bool
398DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
399{
400 // pass it to the memory controller
401 return memory.recvTimingReq(pkt);
402}
403
404void
248{
249 DPRINTF(DRAMSim2, "Retrying\n");
250
251 assert(retryResp);
252 retryResp = false;
253 sendResponse();
254}
255

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397bool
398DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
399{
400 // pass it to the memory controller
401 return memory.recvTimingReq(pkt);
402}
403
404void
405DRAMSim2::MemoryPort::recvRetry()
405DRAMSim2::MemoryPort::recvRespRetry()
406{
406{
407 memory.recvRetry();
407 memory.recvRespRetry();
408}
409
410DRAMSim2*
411DRAMSim2Params::create()
412{
413 return new DRAMSim2(this);
414}
408}
409
410DRAMSim2*
411DRAMSim2Params::create()
412{
413 return new DRAMSim2(this);
414}