dramsim2.cc (10066:06a33d872798) dramsim2.cc (10296:35738ad3c7c6)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "mem/dramsim2.hh"
46#include "sim/system.hh"
47
48DRAMSim2::DRAMSim2(const Params* p) :
49 AbstractMemory(p),
50 port(name() + ".port", *this),
51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "mem/dramsim2.hh"
46#include "sim/system.hh"
47
48DRAMSim2::DRAMSim2(const Params* p) :
49 AbstractMemory(p),
50 port(name() + ".port", *this),
51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
53 retryReq(false), retryResp(false),
53 retryReq(false), retryResp(false), startTick(0),
54 nbrOutstandingReads(0), nbrOutstandingWrites(0),
55 drainManager(NULL),
56 sendResponseEvent(this), tickEvent(this)
57{
58 DPRINTF(DRAMSim2,
59 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
60 wrapper.clockPeriod(), wrapper.queueSize());
61

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86 if (system()->cacheLineSize() != wrapper.burstSize())
87 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
88 wrapper.burstSize(), system()->cacheLineSize());
89}
90
91void
92DRAMSim2::startup()
93{
54 nbrOutstandingReads(0), nbrOutstandingWrites(0),
55 drainManager(NULL),
56 sendResponseEvent(this), tickEvent(this)
57{
58 DPRINTF(DRAMSim2,
59 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
60 wrapper.clockPeriod(), wrapper.queueSize());
61

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86 if (system()->cacheLineSize() != wrapper.burstSize())
87 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
88 wrapper.burstSize(), system()->cacheLineSize());
89}
90
91void
92DRAMSim2::startup()
93{
94 startTick = curTick();
95
94 // kick off the clock ticks
95 schedule(tickEvent, clockEdge());
96}
97
98void
99DRAMSim2::sendResponse()
100{
101 assert(!retryResp);

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282 // @todo the packet is going to be deleted, and the DRAMPacket
283 // is still having a pointer to it
284 pendingDelete.push_back(pkt);
285 }
286}
287
288void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
289{
96 // kick off the clock ticks
97 schedule(tickEvent, clockEdge());
98}
99
100void
101DRAMSim2::sendResponse()
102{
103 assert(!retryResp);

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284 // @todo the packet is going to be deleted, and the DRAMPacket
285 // is still having a pointer to it
286 pendingDelete.push_back(pkt);
287 }
288}
289
290void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
291{
290 assert(cycle == divCeil(curTick(),
292 assert(cycle == divCeil(curTick() - startTick,
291 wrapper.clockPeriod() * SimClock::Int::ns));
292
293 DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
294
295 // get the outstanding reads for the address in question
296 auto p = outstandingReads.find(addr);
297 assert(p != outstandingReads.end());
298

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310 --nbrOutstandingReads;
311
312 // perform the actual memory access
313 accessAndRespond(pkt);
314}
315
316void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
317{
293 wrapper.clockPeriod() * SimClock::Int::ns));
294
295 DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
296
297 // get the outstanding reads for the address in question
298 auto p = outstandingReads.find(addr);
299 assert(p != outstandingReads.end());
300

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312 --nbrOutstandingReads;
313
314 // perform the actual memory access
315 accessAndRespond(pkt);
316}
317
318void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
319{
318 assert(cycle == divCeil(curTick(),
320 assert(cycle == divCeil(curTick() - startTick,
319 wrapper.clockPeriod() * SimClock::Int::ns));
320
321 DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
322
323 // get the outstanding reads for the address in question
324 auto p = outstandingWrites.find(addr);
325 assert(p != outstandingWrites.end());
326

--- 84 unchanged lines hidden --- 		321 wrapper.clockPeriod() * SimClock::Int::ns));
322
323 DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
324
325 // get the outstanding reads for the address in question
326 auto p = outstandingWrites.find(addr);
327 assert(p != outstandingWrites.end());
328

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