1/* 2 * Copyright (c) 2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47 48DRAMSim2::DRAMSim2(const Params* p) : 49 AbstractMemory(p), 50 port(name() + ".port", *this), 51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath, 52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug), 53 retryReq(false), retryResp(false), startTick(0), 54 nbrOutstandingReads(0), nbrOutstandingWrites(0), |
55 sendResponseEvent(this), tickEvent(this) 56{ 57 DPRINTF(DRAMSim2, 58 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n", 59 wrapper.clockPeriod(), wrapper.queueSize()); 60 61 DRAMSim::TransactionCompleteCB* read_cb = 62 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>( --- 49 unchanged lines hidden (view full) --- 112 113 DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n", 114 nbrOutstandingReads, nbrOutstandingWrites, 115 responseQueue.size()); 116 117 if (!responseQueue.empty() && !sendResponseEvent.scheduled()) 118 schedule(sendResponseEvent, curTick()); 119 |
120 if (nbrOutstanding() == 0) 121 signalDrainDone(); |
122 } else { 123 retryResp = true; 124 125 DPRINTF(DRAMSim2, "Waiting for response retry\n"); 126 127 assert(!sendResponseEvent.scheduled()); 128 } 129} --- 200 unchanged lines hidden (view full) --- 330 // what is outstanding 331 p->second.pop(); 332 if (p->second.empty()) 333 outstandingWrites.erase(p); 334 335 assert(nbrOutstandingWrites != 0); 336 --nbrOutstandingWrites; 337 |
338 if (nbrOutstanding() == 0) 339 signalDrainDone(); |
340} 341 342BaseSlavePort& 343DRAMSim2::getSlavePort(const std::string &if_name, PortID idx) 344{ 345 if (if_name != "port") { 346 return MemObject::getSlavePort(if_name, idx); 347 } else { 348 return port; 349 } 350} 351 352unsigned int |
353DRAMSim2::drain() |
354{ 355 // check our outstanding reads and writes and if any they need to 356 // drain |
357 return nbrOutstanding() != 0 ? DrainState::Draining : DrainState::Drained; |
358} 359 360DRAMSim2::MemoryPort::MemoryPort(const std::string& _name, 361 DRAMSim2& _memory) 362 : SlavePort(_name, &_memory), memory(_memory) 363{ } 364 365AddrRangeList --- 37 unchanged lines hidden --- |