1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40#include "DRAMSim2/Callback.h"
41#include "base/callback.hh"
42#include "base/trace.hh"
43#include "debug/DRAMSim2.hh"
44#include "debug/Drain.hh"
45#include "mem/dramsim2.hh"
46#include "sim/system.hh"
47
48DRAMSim2::DRAMSim2(const Params* p) :
49 AbstractMemory(p),
50 port(name() + ".port", *this),
51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
53 retryReq(false), retryResp(false), startTick(0),
54 nbrOutstandingReads(0), nbrOutstandingWrites(0),
55 sendResponseEvent(this), tickEvent(this)
56{
57 DPRINTF(DRAMSim2,
58 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
59 wrapper.clockPeriod(), wrapper.queueSize());
60
61 DRAMSim::TransactionCompleteCB* read_cb =
62 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
63 this, &DRAMSim2::readComplete);
64 DRAMSim::TransactionCompleteCB* write_cb =
65 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
66 this, &DRAMSim2::writeComplete);
67 wrapper.setCallbacks(read_cb, write_cb);
68
69 // Register a callback to compensate for the destructor not
70 // being called. The callback prints the DRAMSim2 stats.
71 Callback* cb = new MakeCallback<DRAMSim2Wrapper,
72 &DRAMSim2Wrapper::printStats>(wrapper);
73 registerExitCallback(cb);
74}
75
76void
77DRAMSim2::init()
78{
79 AbstractMemory::init();
80
81 if (!port.isConnected()) {
82 fatal("DRAMSim2 %s is unconnected!\n", name());
83 } else {
84 port.sendRangeChange();
85 }
86
87 if (system()->cacheLineSize() != wrapper.burstSize())
88 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
89 wrapper.burstSize(), system()->cacheLineSize());
90}
91
92void
93DRAMSim2::startup()
94{
95 startTick = curTick();
96
97 // kick off the clock ticks
98 schedule(tickEvent, clockEdge());
99}
100
101void
102DRAMSim2::sendResponse()
103{
104 assert(!retryResp);
105 assert(!responseQueue.empty());
106
107 DPRINTF(DRAMSim2, "Attempting to send response\n");
108
109 bool success = port.sendTimingResp(responseQueue.front());
110 if (success) {
111 responseQueue.pop_front();
112
113 DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n",
114 nbrOutstandingReads, nbrOutstandingWrites,
115 responseQueue.size());
116
117 if (!responseQueue.empty() && !sendResponseEvent.scheduled())
118 schedule(sendResponseEvent, curTick());
119
120 if (nbrOutstanding() == 0)
121 signalDrainDone();
122 } else {
123 retryResp = true;
124
125 DPRINTF(DRAMSim2, "Waiting for response retry\n");
126
127 assert(!sendResponseEvent.scheduled());
128 }
129}
130
131unsigned int
132DRAMSim2::nbrOutstanding() const
133{
134 return nbrOutstandingReads + nbrOutstandingWrites + responseQueue.size();
135}
136
137void
138DRAMSim2::tick()
139{
140 wrapper.tick();
141
142 // is the connected port waiting for a retry, if so check the
143 // state and send a retry if conditions have changed
144 if (retryReq && nbrOutstanding() < wrapper.queueSize()) {
145 retryReq = false;
146 port.sendRetryReq();
147 }
148
149 schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
150}
151
152Tick
153DRAMSim2::recvAtomic(PacketPtr pkt)
154{
155 access(pkt);
156
157 // 50 ns is just an arbitrary value at this point
| 1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40#include "DRAMSim2/Callback.h"
41#include "base/callback.hh"
42#include "base/trace.hh"
43#include "debug/DRAMSim2.hh"
44#include "debug/Drain.hh"
45#include "mem/dramsim2.hh"
46#include "sim/system.hh"
47
48DRAMSim2::DRAMSim2(const Params* p) :
49 AbstractMemory(p),
50 port(name() + ".port", *this),
51 wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
52 p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
53 retryReq(false), retryResp(false), startTick(0),
54 nbrOutstandingReads(0), nbrOutstandingWrites(0),
55 sendResponseEvent(this), tickEvent(this)
56{
57 DPRINTF(DRAMSim2,
58 "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
59 wrapper.clockPeriod(), wrapper.queueSize());
60
61 DRAMSim::TransactionCompleteCB* read_cb =
62 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
63 this, &DRAMSim2::readComplete);
64 DRAMSim::TransactionCompleteCB* write_cb =
65 new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
66 this, &DRAMSim2::writeComplete);
67 wrapper.setCallbacks(read_cb, write_cb);
68
69 // Register a callback to compensate for the destructor not
70 // being called. The callback prints the DRAMSim2 stats.
71 Callback* cb = new MakeCallback<DRAMSim2Wrapper,
72 &DRAMSim2Wrapper::printStats>(wrapper);
73 registerExitCallback(cb);
74}
75
76void
77DRAMSim2::init()
78{
79 AbstractMemory::init();
80
81 if (!port.isConnected()) {
82 fatal("DRAMSim2 %s is unconnected!\n", name());
83 } else {
84 port.sendRangeChange();
85 }
86
87 if (system()->cacheLineSize() != wrapper.burstSize())
88 fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
89 wrapper.burstSize(), system()->cacheLineSize());
90}
91
92void
93DRAMSim2::startup()
94{
95 startTick = curTick();
96
97 // kick off the clock ticks
98 schedule(tickEvent, clockEdge());
99}
100
101void
102DRAMSim2::sendResponse()
103{
104 assert(!retryResp);
105 assert(!responseQueue.empty());
106
107 DPRINTF(DRAMSim2, "Attempting to send response\n");
108
109 bool success = port.sendTimingResp(responseQueue.front());
110 if (success) {
111 responseQueue.pop_front();
112
113 DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n",
114 nbrOutstandingReads, nbrOutstandingWrites,
115 responseQueue.size());
116
117 if (!responseQueue.empty() && !sendResponseEvent.scheduled())
118 schedule(sendResponseEvent, curTick());
119
120 if (nbrOutstanding() == 0)
121 signalDrainDone();
122 } else {
123 retryResp = true;
124
125 DPRINTF(DRAMSim2, "Waiting for response retry\n");
126
127 assert(!sendResponseEvent.scheduled());
128 }
129}
130
131unsigned int
132DRAMSim2::nbrOutstanding() const
133{
134 return nbrOutstandingReads + nbrOutstandingWrites + responseQueue.size();
135}
136
137void
138DRAMSim2::tick()
139{
140 wrapper.tick();
141
142 // is the connected port waiting for a retry, if so check the
143 // state and send a retry if conditions have changed
144 if (retryReq && nbrOutstanding() < wrapper.queueSize()) {
145 retryReq = false;
146 port.sendRetryReq();
147 }
148
149 schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
150}
151
152Tick
153DRAMSim2::recvAtomic(PacketPtr pkt)
154{
155 access(pkt);
156
157 // 50 ns is just an arbitrary value at this point
|
180 pendingDelete.reset(pkt);
181 return true;
182 }
183
184 // we should not get a new request after committing to retry the
185 // current one, but unfortunately the CPU violates this rule, so
186 // simply ignore it for now
187 if (retryReq)
188 return false;
189
190 // if we cannot accept we need to send a retry once progress can
191 // be made
192 bool can_accept = nbrOutstanding() < wrapper.queueSize();
193
194 // keep track of the transaction
195 if (pkt->isRead()) {
196 if (can_accept) {
197 outstandingReads[pkt->getAddr()].push(pkt);
198
199 // we count a transaction as outstanding until it has left the
200 // queue in the controller, and the response has been sent
201 // back, note that this will differ for reads and writes
202 ++nbrOutstandingReads;
203 }
204 } else if (pkt->isWrite()) {
205 if (can_accept) {
206 outstandingWrites[pkt->getAddr()].push(pkt);
207
208 ++nbrOutstandingWrites;
209
210 // perform the access for writes
211 accessAndRespond(pkt);
212 }
213 } else {
214 // keep it simple and just respond if necessary
215 accessAndRespond(pkt);
216 return true;
217 }
218
219 if (can_accept) {
220 // we should never have a situation when we think there is space,
221 // and there isn't
222 assert(wrapper.canAccept());
223
224 DPRINTF(DRAMSim2, "Enqueueing address %lld\n", pkt->getAddr());
225
226 // @todo what about the granularity here, implicit assumption that
227 // a transaction matches the burst size of the memory (which we
228 // cannot determine without parsing the ini file ourselves)
229 wrapper.enqueue(pkt->isWrite(), pkt->getAddr());
230
231 return true;
232 } else {
233 retryReq = true;
234 return false;
235 }
236}
237
238void
239DRAMSim2::recvRespRetry()
240{
241 DPRINTF(DRAMSim2, "Retrying\n");
242
243 assert(retryResp);
244 retryResp = false;
245 sendResponse();
246}
247
248void
249DRAMSim2::accessAndRespond(PacketPtr pkt)
250{
251 DPRINTF(DRAMSim2, "Access for address %lld\n", pkt->getAddr());
252
253 bool needsResponse = pkt->needsResponse();
254
255 // do the actual memory access which also turns the packet into a
256 // response
257 access(pkt);
258
259 // turn packet around to go back to requester if response expected
260 if (needsResponse) {
261 // access already turned the packet into a response
262 assert(pkt->isResponse());
263 // Here we pay for xbar additional delay and to process the payload
264 // of the packet.
265 Tick time = curTick() + pkt->headerDelay + pkt->payloadDelay;
266 // Reset the timings of the packet
267 pkt->headerDelay = pkt->payloadDelay = 0;
268
269 DPRINTF(DRAMSim2, "Queuing response for address %lld\n",
270 pkt->getAddr());
271
272 // queue it to be sent back
273 responseQueue.push_back(pkt);
274
275 // if we are not already waiting for a retry, or are scheduled
276 // to send a response, schedule an event
277 if (!retryResp && !sendResponseEvent.scheduled())
278 schedule(sendResponseEvent, time);
279 } else {
280 // queue the packet for deletion
281 pendingDelete.reset(pkt);
282 }
283}
284
285void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
286{
287 assert(cycle == divCeil(curTick() - startTick,
288 wrapper.clockPeriod() * SimClock::Int::ns));
289
290 DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
291
292 // get the outstanding reads for the address in question
293 auto p = outstandingReads.find(addr);
294 assert(p != outstandingReads.end());
295
296 // first in first out, which is not necessarily true, but it is
297 // the best we can do at this point
298 PacketPtr pkt = p->second.front();
299 p->second.pop();
300
301 if (p->second.empty())
302 outstandingReads.erase(p);
303
304 // no need to check for drain here as the next call will add a
305 // response to the response queue straight away
306 assert(nbrOutstandingReads != 0);
307 --nbrOutstandingReads;
308
309 // perform the actual memory access
310 accessAndRespond(pkt);
311}
312
313void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
314{
315 assert(cycle == divCeil(curTick() - startTick,
316 wrapper.clockPeriod() * SimClock::Int::ns));
317
318 DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
319
320 // get the outstanding reads for the address in question
321 auto p = outstandingWrites.find(addr);
322 assert(p != outstandingWrites.end());
323
324 // we have already responded, and this is only to keep track of
325 // what is outstanding
326 p->second.pop();
327 if (p->second.empty())
328 outstandingWrites.erase(p);
329
330 assert(nbrOutstandingWrites != 0);
331 --nbrOutstandingWrites;
332
333 if (nbrOutstanding() == 0)
334 signalDrainDone();
335}
336
337BaseSlavePort&
338DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
339{
340 if (if_name != "port") {
341 return MemObject::getSlavePort(if_name, idx);
342 } else {
343 return port;
344 }
345}
346
347DrainState
348DRAMSim2::drain()
349{
350 // check our outstanding reads and writes and if any they need to
351 // drain
352 return nbrOutstanding() != 0 ? DrainState::Draining : DrainState::Drained;
353}
354
355DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
356 DRAMSim2& _memory)
357 : SlavePort(_name, &_memory), memory(_memory)
358{ }
359
360AddrRangeList
361DRAMSim2::MemoryPort::getAddrRanges() const
362{
363 AddrRangeList ranges;
364 ranges.push_back(memory.getAddrRange());
365 return ranges;
366}
367
368Tick
369DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
370{
371 return memory.recvAtomic(pkt);
372}
373
374void
375DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
376{
377 memory.recvFunctional(pkt);
378}
379
380bool
381DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
382{
383 // pass it to the memory controller
384 return memory.recvTimingReq(pkt);
385}
386
387void
388DRAMSim2::MemoryPort::recvRespRetry()
389{
390 memory.recvRespRetry();
391}
392
393DRAMSim2*
394DRAMSim2Params::create()
395{
396 return new DRAMSim2(this);
397}
| 180 pendingDelete.reset(pkt);
181 return true;
182 }
183
184 // we should not get a new request after committing to retry the
185 // current one, but unfortunately the CPU violates this rule, so
186 // simply ignore it for now
187 if (retryReq)
188 return false;
189
190 // if we cannot accept we need to send a retry once progress can
191 // be made
192 bool can_accept = nbrOutstanding() < wrapper.queueSize();
193
194 // keep track of the transaction
195 if (pkt->isRead()) {
196 if (can_accept) {
197 outstandingReads[pkt->getAddr()].push(pkt);
198
199 // we count a transaction as outstanding until it has left the
200 // queue in the controller, and the response has been sent
201 // back, note that this will differ for reads and writes
202 ++nbrOutstandingReads;
203 }
204 } else if (pkt->isWrite()) {
205 if (can_accept) {
206 outstandingWrites[pkt->getAddr()].push(pkt);
207
208 ++nbrOutstandingWrites;
209
210 // perform the access for writes
211 accessAndRespond(pkt);
212 }
213 } else {
214 // keep it simple and just respond if necessary
215 accessAndRespond(pkt);
216 return true;
217 }
218
219 if (can_accept) {
220 // we should never have a situation when we think there is space,
221 // and there isn't
222 assert(wrapper.canAccept());
223
224 DPRINTF(DRAMSim2, "Enqueueing address %lld\n", pkt->getAddr());
225
226 // @todo what about the granularity here, implicit assumption that
227 // a transaction matches the burst size of the memory (which we
228 // cannot determine without parsing the ini file ourselves)
229 wrapper.enqueue(pkt->isWrite(), pkt->getAddr());
230
231 return true;
232 } else {
233 retryReq = true;
234 return false;
235 }
236}
237
238void
239DRAMSim2::recvRespRetry()
240{
241 DPRINTF(DRAMSim2, "Retrying\n");
242
243 assert(retryResp);
244 retryResp = false;
245 sendResponse();
246}
247
248void
249DRAMSim2::accessAndRespond(PacketPtr pkt)
250{
251 DPRINTF(DRAMSim2, "Access for address %lld\n", pkt->getAddr());
252
253 bool needsResponse = pkt->needsResponse();
254
255 // do the actual memory access which also turns the packet into a
256 // response
257 access(pkt);
258
259 // turn packet around to go back to requester if response expected
260 if (needsResponse) {
261 // access already turned the packet into a response
262 assert(pkt->isResponse());
263 // Here we pay for xbar additional delay and to process the payload
264 // of the packet.
265 Tick time = curTick() + pkt->headerDelay + pkt->payloadDelay;
266 // Reset the timings of the packet
267 pkt->headerDelay = pkt->payloadDelay = 0;
268
269 DPRINTF(DRAMSim2, "Queuing response for address %lld\n",
270 pkt->getAddr());
271
272 // queue it to be sent back
273 responseQueue.push_back(pkt);
274
275 // if we are not already waiting for a retry, or are scheduled
276 // to send a response, schedule an event
277 if (!retryResp && !sendResponseEvent.scheduled())
278 schedule(sendResponseEvent, time);
279 } else {
280 // queue the packet for deletion
281 pendingDelete.reset(pkt);
282 }
283}
284
285void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
286{
287 assert(cycle == divCeil(curTick() - startTick,
288 wrapper.clockPeriod() * SimClock::Int::ns));
289
290 DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
291
292 // get the outstanding reads for the address in question
293 auto p = outstandingReads.find(addr);
294 assert(p != outstandingReads.end());
295
296 // first in first out, which is not necessarily true, but it is
297 // the best we can do at this point
298 PacketPtr pkt = p->second.front();
299 p->second.pop();
300
301 if (p->second.empty())
302 outstandingReads.erase(p);
303
304 // no need to check for drain here as the next call will add a
305 // response to the response queue straight away
306 assert(nbrOutstandingReads != 0);
307 --nbrOutstandingReads;
308
309 // perform the actual memory access
310 accessAndRespond(pkt);
311}
312
313void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
314{
315 assert(cycle == divCeil(curTick() - startTick,
316 wrapper.clockPeriod() * SimClock::Int::ns));
317
318 DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
319
320 // get the outstanding reads for the address in question
321 auto p = outstandingWrites.find(addr);
322 assert(p != outstandingWrites.end());
323
324 // we have already responded, and this is only to keep track of
325 // what is outstanding
326 p->second.pop();
327 if (p->second.empty())
328 outstandingWrites.erase(p);
329
330 assert(nbrOutstandingWrites != 0);
331 --nbrOutstandingWrites;
332
333 if (nbrOutstanding() == 0)
334 signalDrainDone();
335}
336
337BaseSlavePort&
338DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
339{
340 if (if_name != "port") {
341 return MemObject::getSlavePort(if_name, idx);
342 } else {
343 return port;
344 }
345}
346
347DrainState
348DRAMSim2::drain()
349{
350 // check our outstanding reads and writes and if any they need to
351 // drain
352 return nbrOutstanding() != 0 ? DrainState::Draining : DrainState::Drained;
353}
354
355DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
356 DRAMSim2& _memory)
357 : SlavePort(_name, &_memory), memory(_memory)
358{ }
359
360AddrRangeList
361DRAMSim2::MemoryPort::getAddrRanges() const
362{
363 AddrRangeList ranges;
364 ranges.push_back(memory.getAddrRange());
365 return ranges;
366}
367
368Tick
369DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
370{
371 return memory.recvAtomic(pkt);
372}
373
374void
375DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
376{
377 memory.recvFunctional(pkt);
378}
379
380bool
381DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
382{
383 // pass it to the memory controller
384 return memory.recvTimingReq(pkt);
385}
386
387void
388DRAMSim2::MemoryPort::recvRespRetry()
389{
390 memory.recvRespRetry();
391}
392
393DRAMSim2*
394DRAMSim2Params::create()
395{
396 return new DRAMSim2(this);
397}
|