drampower.cc (10431:d9415c7f61a9) drampower.cc (10561:e1a853349529)
1/*
2 * Copyright (const c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 141 unchanged lines hidden (view full) ---

150 return p->VDD2 == 0 ? false : true;
151}
152
153uint8_t
154DRAMPower::getDataRate(const DRAMCtrlParams* p)
155{
156 uint32_t burst_cycles = divCeil(p->tBURST, p->tCK);
157 uint8_t data_rate = p->burst_length / burst_cycles;
1/*
2 * Copyright (const c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 141 unchanged lines hidden (view full) ---

150 return p->VDD2 == 0 ? false : true;
151}
152
153uint8_t
154DRAMPower::getDataRate(const DRAMCtrlParams* p)
155{
156 uint32_t burst_cycles = divCeil(p->tBURST, p->tCK);
157 uint8_t data_rate = p->burst_length / burst_cycles;
158 if (data_rate != 1 && data_rate != 2)
159 fatal("Got unexpected data rate %d, should be 1 or 2\n");
158 // 4 for GDDR5
159 if (data_rate != 1 && data_rate != 2 && data_rate != 4)
160 fatal("Got unexpected data rate %d, should be 1 or 2 or 4\n");
160 return data_rate;
161}
161 return data_rate;
162}