drampower.cc (11793:ef606668d247) drampower.cc (12637:bfc3cb9c7e6c)
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Omar Naji
38 */
39
40#include "mem/drampower.hh"
41
42#include "base/intmath.hh"
43#include "sim/core.hh"
44
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Omar Naji
38 */
39
40#include "mem/drampower.hh"
41
42#include "base/intmath.hh"
43#include "sim/core.hh"
44
45using namespace Data;
46
47DRAMPower::DRAMPower(const DRAMCtrlParams* p, bool include_io) :
48 powerlib(libDRAMPower(getMemSpec(p), include_io))
49{
50}
51
52Data::MemArchitectureSpec
53DRAMPower::getArchParams(const DRAMCtrlParams* p)
54{
55 Data::MemArchitectureSpec archSpec;
56 archSpec.burstLength = p->burst_length;
57 archSpec.nbrOfBanks = p->banks_per_rank;
58 // One DRAMPower instance per rank, hence set this to 1
59 archSpec.nbrOfRanks = 1;
60 archSpec.dataRate = getDataRate(p);
61 // For now we can ignore the number of columns and rows as they
62 // are not used in the power calculation.
63 archSpec.nbrOfColumns = 0;
64 archSpec.nbrOfRows = 0;
65 archSpec.width = p->device_bus_width;
66 archSpec.nbrOfBankGroups = p->bank_groups_per_rank;
67 archSpec.dll = p->dll;
68 archSpec.twoVoltageDomains = hasTwoVDD(p);
69 // Keep this disabled for now until the model is firmed up.
70 archSpec.termination = false;
71 return archSpec;
72}
73
74Data::MemTimingSpec
75DRAMPower::getTimingParams(const DRAMCtrlParams* p)
76{
77 // Set the values that are used for power calculations and ignore
78 // the ones only used by the controller functionality in DRAMPower
79
80 // All DRAMPower timings are in clock cycles
81 Data::MemTimingSpec timingSpec;
82 timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK);
83 timingSpec.RCD = divCeil(p->tRCD, p->tCK);
84 timingSpec.RL = divCeil(p->tCL, p->tCK);
85 timingSpec.RP = divCeil(p->tRP, p->tCK);
86 timingSpec.RFC = divCeil(p->tRFC, p->tCK);
87 timingSpec.RAS = divCeil(p->tRAS, p->tCK);
88 // Write latency is read latency - 1 cycle
89 // Source: B.Jacob Memory Systems Cache, DRAM, Disk
90 timingSpec.WL = timingSpec.RL - 1;
91 timingSpec.DQSCK = 0; // ignore for now
92 timingSpec.RTP = divCeil(p->tRTP, p->tCK);
93 timingSpec.WR = divCeil(p->tWR, p->tCK);
94 timingSpec.XP = divCeil(p->tXP, p->tCK);
95 timingSpec.XPDLL = divCeil(p->tXPDLL, p->tCK);
96 timingSpec.XS = divCeil(p->tXS, p->tCK);
97 timingSpec.XSDLL = divCeil(p->tXSDLL, p->tCK);
98
99 // Clock period in ns
100 timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns));
101 assert(timingSpec.clkPeriod != 0);
102 timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
103 return timingSpec;
104}
105
106Data::MemPowerSpec
107DRAMPower::getPowerParams(const DRAMCtrlParams* p)
108{
109 // All DRAMPower currents are in mA
110 Data::MemPowerSpec powerSpec;
111 powerSpec.idd0 = p->IDD0 * 1000;
112 powerSpec.idd02 = p->IDD02 * 1000;
113 powerSpec.idd2p0 = p->IDD2P0 * 1000;
114 powerSpec.idd2p02 = p->IDD2P02 * 1000;
115 powerSpec.idd2p1 = p->IDD2P1 * 1000;
116 powerSpec.idd2p12 = p->IDD2P12 * 1000;
117 powerSpec.idd2n = p->IDD2N * 1000;
118 powerSpec.idd2n2 = p->IDD2N2 * 1000;
119 powerSpec.idd3p0 = p->IDD3P0 * 1000;
120 powerSpec.idd3p02 = p->IDD3P02 * 1000;
121 powerSpec.idd3p1 = p->IDD3P1 * 1000;
122 powerSpec.idd3p12 = p->IDD3P12 * 1000;
123 powerSpec.idd3n = p->IDD3N * 1000;
124 powerSpec.idd3n2 = p->IDD3N2 * 1000;
125 powerSpec.idd4r = p->IDD4R * 1000;
126 powerSpec.idd4r2 = p->IDD4R2 * 1000;
127 powerSpec.idd4w = p->IDD4W * 1000;
128 powerSpec.idd4w2 = p->IDD4W2 * 1000;
129 powerSpec.idd5 = p->IDD5 * 1000;
130 powerSpec.idd52 = p->IDD52 * 1000;
131 powerSpec.idd6 = p->IDD6 * 1000;
132 powerSpec.idd62 = p->IDD62 * 1000;
133 powerSpec.vdd = p->VDD;
134 powerSpec.vdd2 = p->VDD2;
135 return powerSpec;
136}
137
138Data::MemorySpecification
139DRAMPower::getMemSpec(const DRAMCtrlParams* p)
140{
141 Data::MemorySpecification memSpec;
142 memSpec.memArchSpec = getArchParams(p);
143 memSpec.memTimingSpec = getTimingParams(p);
144 memSpec.memPowerSpec = getPowerParams(p);
145 return memSpec;
146}
147
148bool
149DRAMPower::hasTwoVDD(const DRAMCtrlParams* p)
150{
151 return p->VDD2 == 0 ? false : true;
152}
153
154uint8_t
155DRAMPower::getDataRate(const DRAMCtrlParams* p)
156{
157 uint32_t burst_cycles = divCeil(p->tBURST, p->tCK);
158 uint8_t data_rate = p->burst_length / burst_cycles;
159 // 4 for GDDR5
160 if (data_rate != 1 && data_rate != 2 && data_rate != 4)
161 fatal("Got unexpected data rate %d, should be 1 or 2 or 4\n");
162 return data_rate;
163}
45DRAMPower::DRAMPower(const DRAMCtrlParams* p, bool include_io) :
46 powerlib(libDRAMPower(getMemSpec(p), include_io))
47{
48}
49
50Data::MemArchitectureSpec
51DRAMPower::getArchParams(const DRAMCtrlParams* p)
52{
53 Data::MemArchitectureSpec archSpec;
54 archSpec.burstLength = p->burst_length;
55 archSpec.nbrOfBanks = p->banks_per_rank;
56 // One DRAMPower instance per rank, hence set this to 1
57 archSpec.nbrOfRanks = 1;
58 archSpec.dataRate = getDataRate(p);
59 // For now we can ignore the number of columns and rows as they
60 // are not used in the power calculation.
61 archSpec.nbrOfColumns = 0;
62 archSpec.nbrOfRows = 0;
63 archSpec.width = p->device_bus_width;
64 archSpec.nbrOfBankGroups = p->bank_groups_per_rank;
65 archSpec.dll = p->dll;
66 archSpec.twoVoltageDomains = hasTwoVDD(p);
67 // Keep this disabled for now until the model is firmed up.
68 archSpec.termination = false;
69 return archSpec;
70}
71
72Data::MemTimingSpec
73DRAMPower::getTimingParams(const DRAMCtrlParams* p)
74{
75 // Set the values that are used for power calculations and ignore
76 // the ones only used by the controller functionality in DRAMPower
77
78 // All DRAMPower timings are in clock cycles
79 Data::MemTimingSpec timingSpec;
80 timingSpec.RC = divCeil((p->tRAS + p->tRP), p->tCK);
81 timingSpec.RCD = divCeil(p->tRCD, p->tCK);
82 timingSpec.RL = divCeil(p->tCL, p->tCK);
83 timingSpec.RP = divCeil(p->tRP, p->tCK);
84 timingSpec.RFC = divCeil(p->tRFC, p->tCK);
85 timingSpec.RAS = divCeil(p->tRAS, p->tCK);
86 // Write latency is read latency - 1 cycle
87 // Source: B.Jacob Memory Systems Cache, DRAM, Disk
88 timingSpec.WL = timingSpec.RL - 1;
89 timingSpec.DQSCK = 0; // ignore for now
90 timingSpec.RTP = divCeil(p->tRTP, p->tCK);
91 timingSpec.WR = divCeil(p->tWR, p->tCK);
92 timingSpec.XP = divCeil(p->tXP, p->tCK);
93 timingSpec.XPDLL = divCeil(p->tXPDLL, p->tCK);
94 timingSpec.XS = divCeil(p->tXS, p->tCK);
95 timingSpec.XSDLL = divCeil(p->tXSDLL, p->tCK);
96
97 // Clock period in ns
98 timingSpec.clkPeriod = (p->tCK / (double)(SimClock::Int::ns));
99 assert(timingSpec.clkPeriod != 0);
100 timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
101 return timingSpec;
102}
103
104Data::MemPowerSpec
105DRAMPower::getPowerParams(const DRAMCtrlParams* p)
106{
107 // All DRAMPower currents are in mA
108 Data::MemPowerSpec powerSpec;
109 powerSpec.idd0 = p->IDD0 * 1000;
110 powerSpec.idd02 = p->IDD02 * 1000;
111 powerSpec.idd2p0 = p->IDD2P0 * 1000;
112 powerSpec.idd2p02 = p->IDD2P02 * 1000;
113 powerSpec.idd2p1 = p->IDD2P1 * 1000;
114 powerSpec.idd2p12 = p->IDD2P12 * 1000;
115 powerSpec.idd2n = p->IDD2N * 1000;
116 powerSpec.idd2n2 = p->IDD2N2 * 1000;
117 powerSpec.idd3p0 = p->IDD3P0 * 1000;
118 powerSpec.idd3p02 = p->IDD3P02 * 1000;
119 powerSpec.idd3p1 = p->IDD3P1 * 1000;
120 powerSpec.idd3p12 = p->IDD3P12 * 1000;
121 powerSpec.idd3n = p->IDD3N * 1000;
122 powerSpec.idd3n2 = p->IDD3N2 * 1000;
123 powerSpec.idd4r = p->IDD4R * 1000;
124 powerSpec.idd4r2 = p->IDD4R2 * 1000;
125 powerSpec.idd4w = p->IDD4W * 1000;
126 powerSpec.idd4w2 = p->IDD4W2 * 1000;
127 powerSpec.idd5 = p->IDD5 * 1000;
128 powerSpec.idd52 = p->IDD52 * 1000;
129 powerSpec.idd6 = p->IDD6 * 1000;
130 powerSpec.idd62 = p->IDD62 * 1000;
131 powerSpec.vdd = p->VDD;
132 powerSpec.vdd2 = p->VDD2;
133 return powerSpec;
134}
135
136Data::MemorySpecification
137DRAMPower::getMemSpec(const DRAMCtrlParams* p)
138{
139 Data::MemorySpecification memSpec;
140 memSpec.memArchSpec = getArchParams(p);
141 memSpec.memTimingSpec = getTimingParams(p);
142 memSpec.memPowerSpec = getPowerParams(p);
143 return memSpec;
144}
145
146bool
147DRAMPower::hasTwoVDD(const DRAMCtrlParams* p)
148{
149 return p->VDD2 == 0 ? false : true;
150}
151
152uint8_t
153DRAMPower::getDataRate(const DRAMCtrlParams* p)
154{
155 uint32_t burst_cycles = divCeil(p->tBURST, p->tCK);
156 uint8_t data_rate = p->burst_length / burst_cycles;
157 // 4 for GDDR5
158 if (data_rate != 1 && data_rate != 2 && data_rate != 4)
159 fatal("Got unexpected data rate %d, should be 1 or 2 or 4\n");
160 return data_rate;
161}