dram_ctrl.hh (12705:9668a82ead4b) dram_ctrl.hh (12706:456304051464)
1/*
1/*
2 * Copyright (c) 2012-2017 ARM Limited
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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184 public:
185
186 static const uint32_t NO_ROW = -1;
187
188 uint32_t openRow;
189 uint8_t bank;
190 uint8_t bankgr;
191
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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184 public:
185
186 static const uint32_t NO_ROW = -1;
187
188 uint32_t openRow;
189 uint8_t bank;
190 uint8_t bankgr;
191
192 Tick colAllowedAt;
192 Tick rdAllowedAt;
193 Tick wrAllowedAt;
193 Tick preAllowedAt;
194 Tick actAllowedAt;
195
196 uint32_t rowAccesses;
197 uint32_t bytesAccessed;
198
199 Bank() :
200 openRow(NO_ROW), bank(0), bankgr(0),
194 Tick preAllowedAt;
195 Tick actAllowedAt;
196
197 uint32_t rowAccesses;
198 uint32_t bytesAccessed;
199
200 Bank() :
201 openRow(NO_ROW), bank(0), bankgr(0),
201 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
202 rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
202 rowAccesses(0), bytesAccessed(0)
203 { }
204 };
205
206
207 /**
208 * The power state captures the different operational states of
209 * the DRAM and interacts with the bus read/write state machine,

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818 * @param extra_col_delay Any extra delay due to a read/write switch
819 * @return true if a packet is scheduled to a rank which is available else
820 * false
821 */
822 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
823
824 /**
825 * Find which are the earliest banks ready to issue an activate
203 rowAccesses(0), bytesAccessed(0)
204 { }
205 };
206
207
208 /**
209 * The power state captures the different operational states of
210 * the DRAM and interacts with the bus read/write state machine,

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819 * @param extra_col_delay Any extra delay due to a read/write switch
820 * @return true if a packet is scheduled to a rank which is available else
821 * false
822 */
823 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
824
825 /**
826 * Find which are the earliest banks ready to issue an activate
826 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
827 * for the enqueued requests. Assumes maximum of 32 banks per rank
827 * Also checks if the bank is already prepped.
828 *
829 * @param queue Queued requests to consider
828 * Also checks if the bank is already prepped.
829 *
830 * @param queue Queued requests to consider
830 * @param time of seamless burst command
831 * @param min_col_at time of seamless burst command
831 * @return One-hot encoded mask of bank indices
832 * @return boolean indicating burst can issue seamlessly, with no gaps
833 */
832 * @return One-hot encoded mask of bank indices
833 * @return boolean indicating burst can issue seamlessly, with no gaps
834 */
834 std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue,
835 std::pair<std::vector<uint32_t>, bool> minBankPrep(
836 const std::deque<DRAMPacket*>& queue,
835 Tick min_col_at) const;
836
837 /**
838 * Keep track of when row activations happen, in order to enforce
839 * the maximum number of activations in the activation window. The
840 * method updates the time that the banks become available based
841 * on the current limits.
842 *

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934 uint32_t writesThisTime;
935 uint32_t readsThisTime;
936
937 /**
938 * Basic memory timing parameters initialized based on parameter
939 * values.
940 */
941 const Tick M5_CLASS_VAR_USED tCK;
837 Tick min_col_at) const;
838
839 /**
840 * Keep track of when row activations happen, in order to enforce
841 * the maximum number of activations in the activation window. The
842 * method updates the time that the banks become available based
843 * on the current limits.
844 *

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936 uint32_t writesThisTime;
937 uint32_t readsThisTime;
938
939 /**
940 * Basic memory timing parameters initialized based on parameter
941 * values.
942 */
943 const Tick M5_CLASS_VAR_USED tCK;
942 const Tick tWTR;
943 const Tick tRTW;
944 const Tick tCS;
945 const Tick tBURST;
944 const Tick tRTW;
945 const Tick tCS;
946 const Tick tBURST;
947 const Tick tCCD_L_WR;
946 const Tick tCCD_L;
947 const Tick tRCD;
948 const Tick tCL;
949 const Tick tRP;
950 const Tick tRAS;
951 const Tick tWR;
952 const Tick tRTP;
953 const Tick tRFC;
954 const Tick tREFI;
955 const Tick tRRD;
956 const Tick tRRD_L;
957 const Tick tXAW;
958 const Tick tXP;
959 const Tick tXS;
960 const uint32_t activationLimit;
948 const Tick tCCD_L;
949 const Tick tRCD;
950 const Tick tCL;
951 const Tick tRP;
952 const Tick tRAS;
953 const Tick tWR;
954 const Tick tRTP;
955 const Tick tRFC;
956 const Tick tREFI;
957 const Tick tRRD;
958 const Tick tRRD_L;
959 const Tick tXAW;
960 const Tick tXP;
961 const Tick tXS;
962 const uint32_t activationLimit;
963 const Tick rankToRankDly;
964 const Tick wrToRdDly;
965 const Tick rdToWrDly;
961
962 /**
963 * Memory controller configuration initialized based on parameter
964 * values.
965 */
966 Enums::MemSched memSchedPolicy;
967 Enums::AddrMap addrMapping;
968 Enums::PageManage pageMgmt;

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983 /**
984 * Pipeline latency of the backend and PHY. Along with the
985 * frontend contribution, this latency is added to reads serviced
986 * by the DRAM.
987 */
988 const Tick backendLatency;
989
990 /**
966
967 /**
968 * Memory controller configuration initialized based on parameter
969 * values.
970 */
971 Enums::MemSched memSchedPolicy;
972 Enums::AddrMap addrMapping;
973 Enums::PageManage pageMgmt;

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988 /**
989 * Pipeline latency of the backend and PHY. Along with the
990 * frontend contribution, this latency is added to reads serviced
991 * by the DRAM.
992 */
993 const Tick backendLatency;
994
995 /**
991 * Till when has the main data bus been spoken for already?
996 * Till when must we wait before issuing next RD/WR burst?
992 */
997 */
993 Tick busBusyUntil;
998 Tick nextBurstAt;
994
995 Tick prevArrival;
996
997 /**
998 * The soonest you have to start thinking about the next request
999 * is the longest access time that can occur before
999
1000 Tick prevArrival;
1001
1002 /**
1003 * The soonest you have to start thinking about the next request
1004 * is the longest access time that can occur before
1000 * busBusyUntil. Assuming you need to precharge, open a new row,
1005 * nextBurstAt. Assuming you need to precharge, open a new row,
1001 * and access, it is tRP + tRCD + tCL.
1002 */
1003 Tick nextReqTime;
1004
1005 // All statistics that the model needs to capture
1006 Stats::Scalar readReqs;
1007 Stats::Scalar writeReqs;
1008 Stats::Scalar readBursts;

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1007 */
1008 Tick nextReqTime;
1009
1010 // All statistics that the model needs to capture
1011 Stats::Scalar readReqs;
1012 Stats::Scalar writeReqs;
1013 Stats::Scalar readBursts;

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