dram_ctrl.hh (11677:beaf1afe2f83) dram_ctrl.hh (11678:8c6991a00515)
1/*
2 * Copyright (c) 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
1/*
2 * Copyright (c) 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 * Wendy Elsasser
45 */
46
47/**
48 * @file
49 * DRAMCtrl declaration
50 */
51
52#ifndef __MEM_DRAM_CTRL_HH__

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82 * high performance, and lots of flexibility, allowing users to
83 * evaluate the system impact of a wide range of memory technologies,
84 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
85 *
86 * For more details, please see Hansson et al, "Simulating DRAM
87 * controllers for future system architecture exploration",
88 * Proc. ISPASS, 2014. If you use this model as part of your research
89 * please cite the paper.
46 */
47
48/**
49 * @file
50 * DRAMCtrl declaration
51 */
52
53#ifndef __MEM_DRAM_CTRL_HH__

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83 * high performance, and lots of flexibility, allowing users to
84 * evaluate the system impact of a wide range of memory technologies,
85 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
86 *
87 * For more details, please see Hansson et al, "Simulating DRAM
88 * controllers for future system architecture exploration",
89 * Proc. ISPASS, 2014. If you use this model as part of your research
90 * please cite the paper.
91 *
92 * The low-power functionality implements a staggered powerdown
93 * similar to that described in "Optimized Active and Power-Down Mode
94 * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
90 */
91class DRAMCtrl : public AbstractMemory
92{
93
94 private:
95
96 // For now, make use of a queued slave port to avoid dealing with
97 // flow control for the responses being sent back

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135 bool retryWrReq;
136
137 /**
138 * Bus state used to control the read/write switching and drive
139 * the scheduling of the next request.
140 */
141 enum BusState {
142 READ = 0,
95 */
96class DRAMCtrl : public AbstractMemory
97{
98
99 private:
100
101 // For now, make use of a queued slave port to avoid dealing with
102 // flow control for the responses being sent back

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140 bool retryWrReq;
141
142 /**
143 * Bus state used to control the read/write switching and drive
144 * the scheduling of the next request.
145 */
146 enum BusState {
147 READ = 0,
143 READ_TO_WRITE,
144 WRITE,
148 WRITE,
145 WRITE_TO_READ
146 };
147
148 BusState busState;
149
149 };
150
151 BusState busState;
152
153 /* bus state for next request event triggered */
154 BusState busStateNext;
155
150 /**
151 * Simple structure to hold the values needed to keep track of
152 * commands for DRAMPower
153 */
154 struct Command {
155 Data::MemCommand::cmds type;
156 uint8_t bank;
157 Tick timeStamp;

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193 openRow(NO_ROW), bank(0), bankgr(0),
194 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
195 rowAccesses(0), bytesAccessed(0)
196 { }
197 };
198
199
200 /**
156 /**
157 * Simple structure to hold the values needed to keep track of
158 * commands for DRAMPower
159 */
160 struct Command {
161 Data::MemCommand::cmds type;
162 uint8_t bank;
163 Tick timeStamp;

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199 openRow(NO_ROW), bank(0), bankgr(0),
200 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
201 rowAccesses(0), bytesAccessed(0)
202 { }
203 };
204
205
206 /**
207 * The power state captures the different operational states of
208 * the DRAM and interacts with the bus read/write state machine,
209 * and the refresh state machine.
210 *
211 * PWR_IDLE : The idle state in which all banks are closed
212 * From here can transition to: PWR_REF, PWR_ACT,
213 * PWR_PRE_PDN
214 *
215 * PWR_REF : Auto-refresh state. Will transition when refresh is
216 * complete based on power state prior to PWR_REF
217 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
218 * PWR_SREF
219 *
220 * PWR_SREF : Self-refresh state. Entered after refresh if
221 * previous state was PWR_PRE_PDN
222 * From here can transition to: PWR_IDLE
223 *
224 * PWR_PRE_PDN : Precharge power down state
225 * From here can transition to: PWR_REF, PWR_IDLE
226 *
227 * PWR_ACT : Activate state in which one or more banks are open
228 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
229 *
230 * PWR_ACT_PDN : Activate power down state
231 * From here can transition to: PWR_ACT
232 */
233 enum PowerState {
234 PWR_IDLE = 0,
235 PWR_REF,
236 PWR_SREF,
237 PWR_PRE_PDN,
238 PWR_ACT,
239 PWR_ACT_PDN
240 };
241
242 /**
243 * The refresh state is used to control the progress of the
244 * refresh scheduling. When normal operation is in progress the
245 * refresh state is idle. Once tREFI has elasped, a refresh event
246 * is triggered to start the following STM transitions which are
247 * used to issue a refresh and return back to normal operation
248 *
249 * REF_IDLE : IDLE state used during normal operation
250 * From here can transition to: REF_DRAIN
251 *
252 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
253 * after self-refresh exit completes
254 * From here can transition to: REF_DRAIN
255 *
256 * REF_DRAIN : Drain state in which on going accesses complete.
257 * From here can transition to: REF_PD_EXIT
258 *
259 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
260 * Next state dependent on whether banks are open
261 * From here can transition to: REF_PRE, REF_START
262 *
263 * REF_PRE : Close (precharge) all open banks
264 * From here can transition to: REF_START
265 *
266 * REF_START : Issue refresh command and update DRAMPower stats
267 * From here can transition to: REF_RUN
268 *
269 * REF_RUN : Refresh running, waiting for tRFC to expire
270 * From here can transition to: REF_IDLE, REF_SREF_EXIT
271 */
272 enum RefreshState {
273 REF_IDLE = 0,
274 REF_DRAIN,
275 REF_PD_EXIT,
276 REF_SREF_EXIT,
277 REF_PRE,
278 REF_START,
279 REF_RUN
280 };
281
282 /**
201 * Rank class includes a vector of banks. Refresh and Power state
202 * machines are defined per rank. Events required to change the
203 * state of the refresh and power state machine are scheduled per
204 * rank. This class allows the implementation of rank-wise refresh
205 * and rank-wise power-down.
206 */
207 class Rank : public EventManager
208 {
209
210 private:
211
212 /**
283 * Rank class includes a vector of banks. Refresh and Power state
284 * machines are defined per rank. Events required to change the
285 * state of the refresh and power state machine are scheduled per
286 * rank. This class allows the implementation of rank-wise refresh
287 * and rank-wise power-down.
288 */
289 class Rank : public EventManager
290 {
291
292 private:
293
294 /**
213 * The power state captures the different operational states of
214 * the DRAM and interacts with the bus read/write state machine,
215 * and the refresh state machine. In the idle state all banks are
216 * precharged. From there we either go to an auto refresh (as
217 * determined by the refresh state machine), or to a precharge
218 * power down mode. From idle the memory can also go to the active
219 * state (with one or more banks active), and in turn from there
220 * to active power down. At the moment we do not capture the deep
221 * power down and self-refresh state.
222 */
223 enum PowerState {
224 PWR_IDLE = 0,
225 PWR_REF,
226 PWR_PRE_PDN,
227 PWR_ACT,
228 PWR_ACT_PDN
229 };
230
231 /**
232 * The refresh state is used to control the progress of the
233 * refresh scheduling. When normal operation is in progress the
234 * refresh state is idle. From there, it progresses to the refresh
235 * drain state once tREFI has passed. The refresh drain state
236 * captures the DRAM row active state, as it will stay there until
237 * all ongoing accesses complete. Thereafter all banks are
238 * precharged, and lastly, the DRAM is refreshed.
239 */
240 enum RefreshState {
241 REF_IDLE = 0,
242 REF_DRAIN,
243 REF_PRE,
244 REF_RUN
245 };
246
247 /**
248 * A reference to the parent DRAMCtrl instance
249 */
250 DRAMCtrl& memory;
251
252 /**
253 * Since we are taking decisions out of order, we need to keep
295 * A reference to the parent DRAMCtrl instance
296 */
297 DRAMCtrl& memory;
298
299 /**
300 * Since we are taking decisions out of order, we need to keep
254 * track of what power transition is happening at what time, such
255 * that we can go back in time and change history. For example, if
256 * we precharge all banks and schedule going to the idle state, we
257 * might at a later point decide to activate a bank before the
258 * transition to idle would have taken place.
301 * track of what power transition is happening at what time
259 */
260 PowerState pwrStateTrans;
261
262 /**
302 */
303 PowerState pwrStateTrans;
304
305 /**
263 * Current power state.
306 * Previous low-power state, which will be re-entered after refresh.
264 */
307 */
265 PowerState pwrState;
308 PowerState pwrStatePostRefresh;
266
267 /**
268 * Track when we transitioned to the current power state
269 */
270 Tick pwrStateTick;
271
272 /**
309
310 /**
311 * Track when we transitioned to the current power state
312 */
313 Tick pwrStateTick;
314
315 /**
273 * current refresh state
274 */
275 RefreshState refreshState;
276
277 /**
278 * Keep track of when a refresh is due.
279 */
280 Tick refreshDueAt;
281
282 /*
283 * Command energies
284 */
285 Stats::Scalar actEnergy;

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293 */
294 Stats::Scalar actBackEnergy;
295
296 /*
297 * Precharge Background Energy
298 */
299 Stats::Scalar preBackEnergy;
300
316 * Keep track of when a refresh is due.
317 */
318 Tick refreshDueAt;
319
320 /*
321 * Command energies
322 */
323 Stats::Scalar actEnergy;

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331 */
332 Stats::Scalar actBackEnergy;
333
334 /*
335 * Precharge Background Energy
336 */
337 Stats::Scalar preBackEnergy;
338
339 /*
340 * Active Power-Down Energy
341 */
342 Stats::Scalar actPowerDownEnergy;
343
344 /*
345 * Precharge Power-Down Energy
346 */
347 Stats::Scalar prePowerDownEnergy;
348
349 /*
350 * self Refresh Energy
351 */
352 Stats::Scalar selfRefreshEnergy;
353
301 Stats::Scalar totalEnergy;
302 Stats::Scalar averagePower;
303
304 /**
354 Stats::Scalar totalEnergy;
355 Stats::Scalar averagePower;
356
357 /**
358 * Stat to track total DRAM idle time
359 *
360 */
361 Stats::Scalar totalIdleTime;
362
363 /**
305 * Track time spent in each power state.
306 */
307 Stats::Vector pwrStateTime;
308
309 /**
310 * Function to update Power Stats
311 */
312 void updatePowerStats();

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318 * @param pwr_state Power state to transition to
319 * @param tick Tick when transition should take place
320 */
321 void schedulePowerEvent(PowerState pwr_state, Tick tick);
322
323 public:
324
325 /**
364 * Track time spent in each power state.
365 */
366 Stats::Vector pwrStateTime;
367
368 /**
369 * Function to update Power Stats
370 */
371 void updatePowerStats();

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377 * @param pwr_state Power state to transition to
378 * @param tick Tick when transition should take place
379 */
380 void schedulePowerEvent(PowerState pwr_state, Tick tick);
381
382 public:
383
384 /**
385 * Current power state.
386 */
387 PowerState pwrState;
388
389 /**
390 * current refresh state
391 */
392 RefreshState refreshState;
393
394 /**
395 * rank is in or transitioning to power-down or self-refresh
396 */
397 bool inLowPowerState;
398
399 /**
326 * Current Rank index
327 */
328 uint8_t rank;
329
400 * Current Rank index
401 */
402 uint8_t rank;
403
404 /**
405 * Track number of packets in read queue going to this rank
406 */
407 uint32_t readEntries;
408
409 /**
410 * Track number of packets in write queue going to this rank
411 */
412 uint32_t writeEntries;
413
330 /**
414 /**
415 * Number of ACT, RD, and WR events currently scheduled
416 * Incremented when a refresh event is started as well
417 * Used to determine when a low-power state can be entered
418 */
419 uint8_t outstandingEvents;
420
421 /**
422 * delay power-down and self-refresh exit until this requirement is met
423 */
424 Tick wakeUpAllowedAt;
425
426 /**
331 * One DRAMPower instance per rank
332 */
333 DRAMPower power;
334
335 /**
336 * List of comamnds issued, to be sent to DRAMPpower at refresh
337 * and stats dump. Keep commands here since commands to different
338 * banks are added out of order. Will only pass commands up to

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372
373 /**
374 * Stop the refresh events.
375 */
376 void suspend();
377
378 /**
379 * Check if the current rank is available for scheduling.
427 * One DRAMPower instance per rank
428 */
429 DRAMPower power;
430
431 /**
432 * List of comamnds issued, to be sent to DRAMPpower at refresh
433 * and stats dump. Keep commands here since commands to different
434 * banks are added out of order. Will only pass commands up to

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468
469 /**
470 * Stop the refresh events.
471 */
472 void suspend();
473
474 /**
475 * Check if the current rank is available for scheduling.
476 * Rank will be unavailable if refresh is ongoing.
477 * This includes refresh events explicitly scheduled from the the
478 * controller or memory initiated events which will occur during
479 * self-refresh mode.
380 *
381 * @param Return true if the rank is idle from a refresh point of view
382 */
383 bool isAvailable() const { return refreshState == REF_IDLE; }
384
385 /**
386 * Check if the current rank has all banks closed and is not
387 * in a low power state
388 *
389 * @param Return true if the rank is idle from a bank
390 * and power point of view
391 */
392 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
393
394 /**
480 *
481 * @param Return true if the rank is idle from a refresh point of view
482 */
483 bool isAvailable() const { return refreshState == REF_IDLE; }
484
485 /**
486 * Check if the current rank has all banks closed and is not
487 * in a low power state
488 *
489 * @param Return true if the rank is idle from a bank
490 * and power point of view
491 */
492 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
493
494 /**
495 * Trigger a self-refresh exit if there are entries enqueued
496 * Exit if there are any read entries regardless of the bus state.
497 * If we are currently issuing write commands, exit if we have any
498 * write commands enqueued as well.
499 * Could expand this in the future to analyze state of entire queue
500 * if needed.
501 *
502 * @return boolean indicating self-refresh exit should be scheduled
503 */
504 bool forceSelfRefreshExit() const {
505 return (readEntries != 0) ||
506 ((memory.busStateNext == WRITE) && (writeEntries != 0));
507 }
508
509 /**
510 * Check if the current rank is idle and should enter a low-pwer state
511 *
512 * @param Return true if the there are no read commands in Q
513 * and there are no outstanding events
514 */
515 bool lowPowerEntryReady() const;
516
517 /**
395 * Let the rank check if it was waiting for requests to drain
396 * to allow it to transition states.
397 */
398 void checkDrainDone();
399
400 /**
401 * Push command out of cmdList queue that are scheduled at
402 * or before curTick() to DRAMPower library

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410 */
411 void regStats();
412
413 /**
414 * Computes stats just prior to dump event
415 */
416 void computeStats();
417
518 * Let the rank check if it was waiting for requests to drain
519 * to allow it to transition states.
520 */
521 void checkDrainDone();
522
523 /**
524 * Push command out of cmdList queue that are scheduled at
525 * or before curTick() to DRAMPower library

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533 */
534 void regStats();
535
536 /**
537 * Computes stats just prior to dump event
538 */
539 void computeStats();
540
541 /**
542 * Schedule a transition to power-down (sleep)
543 *
544 * @param pwr_state Power state to transition to
545 * @param tick Absolute tick when transition should take place
546 */
547 void powerDownSleep(PowerState pwr_state, Tick tick);
548
549 /**
550 * schedule and event to wake-up from power-down or self-refresh
551 * and update bank timing parameters
552 *
553 * @param exit_delay Relative tick defining the delay required between
554 * low-power exit and the next command
555 */
556 void scheduleWakeUpEvent(Tick exit_delay);
557
558 void processWriteDoneEvent();
559 EventWrapper<Rank, &Rank::processWriteDoneEvent>
560 writeDoneEvent;
561
418 void processActivateEvent();
419 EventWrapper<Rank, &Rank::processActivateEvent>
420 activateEvent;
421
422 void processPrechargeEvent();
423 EventWrapper<Rank, &Rank::processPrechargeEvent>
424 prechargeEvent;
425
426 void processRefreshEvent();
427 EventWrapper<Rank, &Rank::processRefreshEvent>
428 refreshEvent;
429
430 void processPowerEvent();
431 EventWrapper<Rank, &Rank::processPowerEvent>
432 powerEvent;
433
562 void processActivateEvent();
563 EventWrapper<Rank, &Rank::processActivateEvent>
564 activateEvent;
565
566 void processPrechargeEvent();
567 EventWrapper<Rank, &Rank::processPrechargeEvent>
568 prechargeEvent;
569
570 void processRefreshEvent();
571 EventWrapper<Rank, &Rank::processRefreshEvent>
572 refreshEvent;
573
574 void processPowerEvent();
575 EventWrapper<Rank, &Rank::processPowerEvent>
576 powerEvent;
577
578 void processWakeUpEvent();
579 EventWrapper<Rank, &Rank::processWakeUpEvent>
580 wakeUpEvent;
581
434 };
435
436 // define the process to compute stats on simulation exit
437 // defined per rank as the per rank stats are based on state
438 // transition and periodically updated, requiring re-sync at
439 // exit.
440 class RankDumpCallback : public Callback
441 {

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583
584 // define the process to compute stats on simulation exit
585 // defined per rank as the per rank stats are based on state
586 // transition and periodically updated, requiring re-sync at
587 // exit.
588 class RankDumpCallback : public Callback
589 {

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