dram_ctrl.hh (11675:60d18201148d) | dram_ctrl.hh (11676:8a882e297eb2) |
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1/* 2 * Copyright (c) 2012-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 368 unchanged lines hidden (view full) --- 377 /** 378 * Check if the current rank is available for scheduling. 379 * 380 * @param Return true if the rank is idle from a refresh point of view 381 */ 382 bool isAvailable() const { return refreshState == REF_IDLE; } 383 384 /** | 1/* 2 * Copyright (c) 2012-2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 368 unchanged lines hidden (view full) --- 377 /** 378 * Check if the current rank is available for scheduling. 379 * 380 * @param Return true if the rank is idle from a refresh point of view 381 */ 382 bool isAvailable() const { return refreshState == REF_IDLE; } 383 384 /** |
385 * Check if the current rank has all banks closed and is not 386 * in a low power state 387 * 388 * @param Return true if the rank is idle from a bank 389 * and power point of view 390 */ 391 bool inPwrIdleState() const { return pwrState == PWR_IDLE; } 392 393 /** |
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385 * Let the rank check if it was waiting for requests to drain 386 * to allow it to transition states. 387 */ 388 void checkDrainDone(); 389 390 /** 391 * Push command out of cmdList queue that are scheduled at 392 * or before curTick() to DRAMPower library --- 515 unchanged lines hidden (view full) --- 908 909 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 910 PortID idx = InvalidPortID) override; 911 912 virtual void init() override; 913 virtual void startup() override; 914 virtual void drainResume() override; 915 | 394 * Let the rank check if it was waiting for requests to drain 395 * to allow it to transition states. 396 */ 397 void checkDrainDone(); 398 399 /** 400 * Push command out of cmdList queue that are scheduled at 401 * or before curTick() to DRAMPower library --- 515 unchanged lines hidden (view full) --- 917 918 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 919 PortID idx = InvalidPortID) override; 920 921 virtual void init() override; 922 virtual void startup() override; 923 virtual void drainResume() override; 924 |
925 /** 926 * Return true once refresh is complete for all ranks and there are no 927 * additional commands enqueued. (only evaluated when draining) 928 * This will ensure that all banks are closed, power state is IDLE, and 929 * power stats have been updated 930 * 931 * @return true if all ranks have refreshed, with no commands enqueued 932 * 933 */ 934 bool allRanksDrained() const; 935 |
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916 protected: 917 918 Tick recvAtomic(PacketPtr pkt); 919 void recvFunctional(PacketPtr pkt); 920 bool recvTimingReq(PacketPtr pkt); 921 922}; 923 924#endif //__MEM_DRAM_CTRL_HH__ | 936 protected: 937 938 Tick recvAtomic(PacketPtr pkt); 939 void recvFunctional(PacketPtr pkt); 940 bool recvTimingReq(PacketPtr pkt); 941 942}; 943 944#endif //__MEM_DRAM_CTRL_HH__ |