dram_ctrl.hh (11673:9f3ccf96bb5a) dram_ctrl.hh (11675:60d18201148d)
1/*
1/*
2 * Copyright (c) 2012-2015 ARM Limited
2 * Copyright (c) 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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142 READ_TO_WRITE,
143 WRITE,
144 WRITE_TO_READ
145 };
146
147 BusState busState;
148
149 /**
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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142 READ_TO_WRITE,
143 WRITE,
144 WRITE_TO_READ
145 };
146
147 BusState busState;
148
149 /**
150 * Simple structure to hold the values needed to keep track of
151 * commands for DRAMPower
152 */
153 struct Command {
154 Data::MemCommand::cmds type;
155 uint8_t bank;
156 Tick timeStamp;
157
158 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
159 Tick time_stamp)
160 : type(_type), bank(_bank), timeStamp(time_stamp)
161 { }
162 };
163
164 /**
150 * A basic class to track the bank state, i.e. what row is
151 * currently open (if any), when is the bank free to accept a new
152 * column (read/write) command, when can it be precharged, and
153 * when can it be activated.
154 *
155 * The bank also keeps track of how many bytes have been accessed
156 * in the open row since it was opened.
157 */

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312 uint8_t rank;
313
314 /**
315 * One DRAMPower instance per rank
316 */
317 DRAMPower power;
318
319 /**
165 * A basic class to track the bank state, i.e. what row is
166 * currently open (if any), when is the bank free to accept a new
167 * column (read/write) command, when can it be precharged, and
168 * when can it be activated.
169 *
170 * The bank also keeps track of how many bytes have been accessed
171 * in the open row since it was opened.
172 */

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327 uint8_t rank;
328
329 /**
330 * One DRAMPower instance per rank
331 */
332 DRAMPower power;
333
334 /**
335 * List of comamnds issued, to be sent to DRAMPpower at refresh
336 * and stats dump. Keep commands here since commands to different
337 * banks are added out of order. Will only pass commands up to
338 * curTick() to DRAMPower after sorting.
339 */
340 std::vector<Command> cmdList;
341
342 /**
320 * Vector of Banks. Each rank is made of several devices which in
321 * term are made from several banks.
322 */
323 std::vector<Bank> banks;
324
325 /**
326 * To track number of banks which are currently active for
327 * this rank.

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359 bool isAvailable() const { return refreshState == REF_IDLE; }
360
361 /**
362 * Let the rank check if it was waiting for requests to drain
363 * to allow it to transition states.
364 */
365 void checkDrainDone();
366
343 * Vector of Banks. Each rank is made of several devices which in
344 * term are made from several banks.
345 */
346 std::vector<Bank> banks;
347
348 /**
349 * To track number of banks which are currently active for
350 * this rank.

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382 bool isAvailable() const { return refreshState == REF_IDLE; }
383
384 /**
385 * Let the rank check if it was waiting for requests to drain
386 * to allow it to transition states.
387 */
388 void checkDrainDone();
389
390 /**
391 * Push command out of cmdList queue that are scheduled at
392 * or before curTick() to DRAMPower library
393 * All commands before curTick are guaranteed to be complete
394 * and can safely be flushed.
395 */
396 void flushCmdList();
397
367 /*
368 * Function to register Stats
369 */
370 void regStats();
371
372 void processActivateEvent();
373 EventWrapper<Rank, &Rank::processActivateEvent>
374 activateEvent;

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852 * result of the energy values coming from DRAMPower, and there
853 * is currently no support for resetting the state.
854 *
855 * @param rank Currrent rank
856 */
857 void updatePowerStats(Rank& rank_ref);
858
859 /**
398 /*
399 * Function to register Stats
400 */
401 void regStats();
402
403 void processActivateEvent();
404 EventWrapper<Rank, &Rank::processActivateEvent>
405 activateEvent;

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883 * result of the energy values coming from DRAMPower, and there
884 * is currently no support for resetting the state.
885 *
886 * @param rank Currrent rank
887 */
888 void updatePowerStats(Rank& rank_ref);
889
890 /**
860 * Function for sorting commands in the command list of DRAMPower.
891 * Function for sorting Command structures based on timeStamp
861 *
892 *
862 * @param a Memory Command in command list of DRAMPower library
863 * @param next Memory Command in command list of DRAMPower
864 * @return true if timestamp of Command 1 < timestamp of Command 2
893 * @param a Memory Command
894 * @param next Memory Command
895 * @return true if timeStamp of Command 1 < timeStamp of Command 2
865 */
896 */
866 static bool sortTime(const Data::MemCommand& m1,
867 const Data::MemCommand& m2) {
868 return m1.getTimeInt64() < m2.getTimeInt64();
897 static bool sortTime(const Command& cmd, const Command& cmd_next) {
898 return cmd.timeStamp < cmd_next.timeStamp;
869 };
870
899 };
900
871
872 public:
873
874 void regStats() override;
875
876 DRAMCtrl(const DRAMCtrlParams* p);
877
878 DrainState drain() override;
879

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902
903 void regStats() override;
904
905 DRAMCtrl(const DRAMCtrlParams* p);
906
907 DrainState drain() override;
908

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