| dram_ctrl.hh (10913:38dbdeea7f1f) | dram_ctrl.hh (11168:f98eb2da15a4) |
|---|---|
| 1/* 2 * Copyright (c) 2012-2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 858 unchanged lines hidden (view full) --- 867 868 869 public: 870 871 void regStats(); 872 873 DRAMCtrl(const DRAMCtrlParams* p); 874 | 1/* 2 * Copyright (c) 2012-2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 858 unchanged lines hidden (view full) --- 867 868 869 public: 870 871 void regStats(); 872 873 DRAMCtrl(const DRAMCtrlParams* p); 874 |
| 875 DrainState drain() M5_ATTR_OVERRIDE; | 875 DrainState drain() override; |
| 876 877 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 878 PortID idx = InvalidPortID); 879 | 876 877 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 878 PortID idx = InvalidPortID); 879 |
| 880 virtual void init() M5_ATTR_OVERRIDE; 881 virtual void startup() M5_ATTR_OVERRIDE; 882 virtual void drainResume() M5_ATTR_OVERRIDE; | 880 virtual void init() override; 881 virtual void startup() override; 882 virtual void drainResume() override; |
| 883 884 protected: 885 886 Tick recvAtomic(PacketPtr pkt); 887 void recvFunctional(PacketPtr pkt); 888 bool recvTimingReq(PacketPtr pkt); 889 890}; 891 892#endif //__MEM_DRAM_CTRL_HH__ | 883 884 protected: 885 886 Tick recvAtomic(PacketPtr pkt); 887 void recvFunctional(PacketPtr pkt); 888 bool recvTimingReq(PacketPtr pkt); 889 890}; 891 892#endif //__MEM_DRAM_CTRL_HH__ |