dram_ctrl.hh (10713:eddb533708cb) dram_ctrl.hh (10889:c4c13fced000)
1/*
1/*
2 * Copyright (c) 2012-2014 ARM Limited
2 * Copyright (c) 2012-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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48 * DRAMCtrl declaration
49 */
50
51#ifndef __MEM_DRAM_CTRL_HH__
52#define __MEM_DRAM_CTRL_HH__
53
54#include <deque>
55#include <string>
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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48 * DRAMCtrl declaration
49 */
50
51#ifndef __MEM_DRAM_CTRL_HH__
52#define __MEM_DRAM_CTRL_HH__
53
54#include <deque>
55#include <string>
56#include <unordered_set>
56
57#include "base/statistics.hh"
58#include "enums/AddrMap.hh"
59#include "enums/MemSched.hh"
60#include "enums/PageManage.hh"
61#include "mem/abstract_mem.hh"
62#include "mem/qport.hh"
63#include "params/DRAMCtrl.hh"

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632 Tick pre_at, bool trace = true);
633
634 /**
635 * Used for debugging to observe the contents of the queues.
636 */
637 void printQs() const;
638
639 /**
57
58#include "base/statistics.hh"
59#include "enums/AddrMap.hh"
60#include "enums/MemSched.hh"
61#include "enums/PageManage.hh"
62#include "mem/abstract_mem.hh"
63#include "mem/qport.hh"
64#include "params/DRAMCtrl.hh"

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633 Tick pre_at, bool trace = true);
634
635 /**
636 * Used for debugging to observe the contents of the queues.
637 */
638 void printQs() const;
639
640 /**
641 * Burst-align an address.
642 *
643 * @param addr The potentially unaligned address
644 *
645 * @return An address aligned to a DRAM burst
646 */
647 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
648
649 /**
640 * The controller's main read and write queues
641 */
642 std::deque<DRAMPacket*> readQueue;
643 std::deque<DRAMPacket*> writeQueue;
644
645 /**
650 * The controller's main read and write queues
651 */
652 std::deque<DRAMPacket*> readQueue;
653 std::deque<DRAMPacket*> writeQueue;
654
655 /**
656 * To avoid iterating over the write queue to check for
657 * overlapping transactions, maintain a set of burst addresses
658 * that are currently queued. Since we merge writes to the same
659 * location we never have more than one address to the same burst
660 * address.
661 */
662 std::unordered_set<Addr> isInWriteQueue;
663
664 /**
646 * Response queue where read packets wait after we're done working
647 * with them, but it's not time to send the response yet. The
648 * responses are stored seperately mostly to keep the code clean
649 * and help with events scheduling. For all logical purposes such
650 * as sizing the read queue, this and the main read queue need to
651 * be added together.
652 */
653 std::deque<DRAMPacket*> respQueue;

--- 227 unchanged lines hidden --- 		665 * Response queue where read packets wait after we're done working
666 * with them, but it's not time to send the response yet. The
667 * responses are stored seperately mostly to keep the code clean
668 * and help with events scheduling. For all logical purposes such
669 * as sizing the read queue, this and the main read queue need to
670 * be added together.
671 */
672 std::deque<DRAMPacket*> respQueue;

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