dram_ctrl.hh (10287:4966471a1ba1) dram_ctrl.hh (10393:0fafa62b6c01)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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363 */
364 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
365 bool isRead);
366
367 /**
368 * The memory schduler/arbiter - picks which request needs to
369 * go next, based on the specified policy such as FCFS or FR-FCFS
370 * and moves it to the head of the queue.
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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363 */
364 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
365 bool isRead);
366
367 /**
368 * The memory schduler/arbiter - picks which request needs to
369 * go next, based on the specified policy such as FCFS or FR-FCFS
370 * and moves it to the head of the queue.
371 * Prioritizes accesses to the same rank as previous burst unless
372 * controller is switching command type.
373 *
374 * @param queue Queued requests to consider
375 * @param switched_cmd_type Command type is changing
371 */
376 */
372 void chooseNext(std::deque& queue);
377 void chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type);
373
374 /**
375 * For FR-FCFS policy reorder the read/write queue depending on row buffer
376 * hits and earliest banks available in DRAM
378
379 /**
380 * For FR-FCFS policy reorder the read/write queue depending on row buffer
381 * hits and earliest banks available in DRAM
382 * Prioritizes accesses to the same rank as previous burst unless
383 * controller is switching command type.
384 *
385 * @param queue Queued requests to consider
386 * @param switched_cmd_type Command type is changing
377 */
387 */
378 void reorderQueue(std::deque& queue);
388 void reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type);
379
380 /**
381 * Find which are the earliest banks ready to issue an activate
382 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
389
390 /**
391 * Find which are the earliest banks ready to issue an activate
392 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
393 * Also checks if the bank is already prepped.
383 *
394 *
384 * @param Queued requests to consider
395 * @param queue Queued requests to consider
396 * @param switched_cmd_type Command type is changing
385 * @return One-hot encoded mask of bank indices
386 */
397 * @return One-hot encoded mask of bank indices
398 */
387 uint64_t minBankActAt(const std::deque<DRAMPacket*>& queue) const;
399 uint64_t minBankPrep(const std::deque<DRAMPacket*>& queue,
400 bool switched_cmd_type) const;
388
389 /**
390 * Keep track of when row activations happen, in order to enforce
391 * the maximum number of activations in the activation window. The
392 * method updates the time that the banks become available based
393 * on the current limits.
394 *
395 * @param bank Reference to the bank

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470
471 /**
472 * Basic memory timing parameters initialized based on parameter
473 * values.
474 */
475 const Tick M5_CLASS_VAR_USED tCK;
476 const Tick tWTR;
477 const Tick tRTW;
401
402 /**
403 * Keep track of when row activations happen, in order to enforce
404 * the maximum number of activations in the activation window. The
405 * method updates the time that the banks become available based
406 * on the current limits.
407 *
408 * @param bank Reference to the bank

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483
484 /**
485 * Basic memory timing parameters initialized based on parameter
486 * values.
487 */
488 const Tick M5_CLASS_VAR_USED tCK;
489 const Tick tWTR;
490 const Tick tRTW;
491 const Tick tCS;
478 const Tick tBURST;
479 const Tick tRCD;
480 const Tick tCL;
481 const Tick tRP;
482 const Tick tRAS;
483 const Tick tWR;
484 const Tick tRTP;
485 const Tick tRFC;

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659 Stats::Vector pwrStateTime;
660
661 // Track when we transitioned to the current power state
662 Tick pwrStateTick;
663
664 // To track number of banks which are currently active
665 unsigned int numBanksActive;
666
492 const Tick tBURST;
493 const Tick tRCD;
494 const Tick tCL;
495 const Tick tRP;
496 const Tick tRAS;
497 const Tick tWR;
498 const Tick tRTP;
499 const Tick tRFC;

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673 Stats::Vector pwrStateTime;
674
675 // Track when we transitioned to the current power state
676 Tick pwrStateTick;
677
678 // To track number of banks which are currently active
679 unsigned int numBanksActive;
680
681 // Holds the value of the rank of burst issued
682 uint8_t activeRank;
683
667 /** @todo this is a temporary workaround until the 4-phase code is
668 * committed. upstream caches needs this packet until true is returned, so
669 * hold onto it for deletion until a subsequent call
670 */
671 std::vector<PacketPtr> pendingDelete;
672
673 public:
674

--- 21 unchanged lines hidden --- 		684 /** @todo this is a temporary workaround until the 4-phase code is
685 * committed. upstream caches needs this packet until true is returned, so
686 * hold onto it for deletion until a subsequent call
687 */
688 std::vector<PacketPtr> pendingDelete;
689
690 public:
691

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