dram_ctrl.hh (10246:e0e3efe3b1d5) | dram_ctrl.hh (10247:0ad233f0a77d) |
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1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 387 unchanged lines hidden (view full) --- 396 */ 397 void activateBank(Bank& bank, Tick act_tick, uint32_t row); 398 399 /** 400 * Precharge a given bank and also update when the precharge is 401 * done. This will also deal with any stats related to the 402 * accesses to the open page. 403 * | 1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 387 unchanged lines hidden (view full) --- 396 */ 397 void activateBank(Bank& bank, Tick act_tick, uint32_t row); 398 399 /** 400 * Precharge a given bank and also update when the precharge is 401 * done. This will also deal with any stats related to the 402 * accesses to the open page. 403 * |
404 * @param bank The bank to precharge | 404 * @param bank_ref The bank to precharge |
405 * @param pre_at Time when the precharge takes place | 405 * @param pre_at Time when the precharge takes place |
406 * @param trace Is this an auto precharge then do not add to trace |
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406 */ | 407 */ |
407 void prechargeBank(Bank& bank, Tick pre_at); | 408 void prechargeBank(Bank& bank_ref, Tick pre_at, bool trace = true); |
408 409 /** 410 * Used for debugging to observe the contents of the queues. 411 */ 412 void printQs() const; 413 414 /** 415 * The controller's main read and write queues --- 276 unchanged lines hidden --- | 409 410 /** 411 * Used for debugging to observe the contents of the queues. 412 */ 413 void printQs() const; 414 415 /** 416 * The controller's main read and write queues --- 276 unchanged lines hidden --- |