dram_ctrl.hh (10210:793e5ff26e0b) dram_ctrl.hh (10211:e084db2b1527)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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117
118 /**
119 * Remember if we have to retry a request when available.
120 */
121 bool retryRdReq;
122 bool retryWrReq;
123
124 /**
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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117
118 /**
119 * Remember if we have to retry a request when available.
120 */
121 bool retryRdReq;
122 bool retryWrReq;
123
124 /**
125 * Remember that a row buffer hit occured
126 */
127 bool rowHitFlag;
128
129 /**
130 * Bus state used to control the read/write switching and drive
131 * the scheduling of the next request.
132 */
133 enum BusState {
134 READ = 0,
135 READ_TO_WRITE,
136 WRITE,
137 WRITE_TO_READ
138 };
139
140 BusState busState;
141
142 /** List to keep track of activate ticks */
143 std::vector<std::deque<Tick>> actTicks;
144
145 /**
146 * A basic class to track the bank state, i.e. what row is
147 * currently open (if any), when is the bank free to accept a new
125 * Bus state used to control the read/write switching and drive
126 * the scheduling of the next request.
127 */
128 enum BusState {
129 READ = 0,
130 READ_TO_WRITE,
131 WRITE,
132 WRITE_TO_READ
133 };
134
135 BusState busState;
136
137 /** List to keep track of activate ticks */
138 std::vector<std::deque<Tick>> actTicks;
139
140 /**
141 * A basic class to track the bank state, i.e. what row is
142 * currently open (if any), when is the bank free to accept a new
148 * command, when can it be precharged, and when can it be
149 * activated.
143 * column (read/write) command, when can it be precharged, and
144 * when can it be activated.
150 *
151 * The bank also keeps track of how many bytes have been accessed
152 * in the open row since it was opened.
153 */
154 class Bank
155 {
156
157 public:
158
159 static const uint32_t NO_ROW = -1;
160
161 uint32_t openRow;
162
145 *
146 * The bank also keeps track of how many bytes have been accessed
147 * in the open row since it was opened.
148 */
149 class Bank
150 {
151
152 public:
153
154 static const uint32_t NO_ROW = -1;
155
156 uint32_t openRow;
157
163 Tick freeAt;
158 Tick colAllowedAt;
164 Tick preAllowedAt;
165 Tick actAllowedAt;
166
167 uint32_t rowAccesses;
168 uint32_t bytesAccessed;
169
170 Bank() :
159 Tick preAllowedAt;
160 Tick actAllowedAt;
161
162 uint32_t rowAccesses;
163 uint32_t bytesAccessed;
164
165 Bank() :
171 openRow(NO_ROW), freeAt(0), preAllowedAt(0), actAllowedAt(0),
166 openRow(NO_ROW), colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
172 rowAccesses(0), bytesAccessed(0)
173 { }
174 };
175
176 /**
177 * A burst helper helps organize and manage a packet that is larger than
178 * the DRAM burst size. A system packet that is larger than the burst size
179 * is split into multiple DRAM packets and all those DRAM packets point to

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367 /**
368 * The memory schduler/arbiter - picks which request needs to
369 * go next, based on the specified policy such as FCFS or FR-FCFS
370 * and moves it to the head of the queue.
371 */
372 void chooseNext(std::deque<DRAMPacket*>& queue);
373
374 /**
167 rowAccesses(0), bytesAccessed(0)
168 { }
169 };
170
171 /**
172 * A burst helper helps organize and manage a packet that is larger than
173 * the DRAM burst size. A system packet that is larger than the burst size
174 * is split into multiple DRAM packets and all those DRAM packets point to

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362 /**
363 * The memory schduler/arbiter - picks which request needs to
364 * go next, based on the specified policy such as FCFS or FR-FCFS
365 * and moves it to the head of the queue.
366 */
367 void chooseNext(std::deque<DRAMPacket*>& queue);
368
369 /**
375 *Looks at the state of the banks, channels, row buffer hits etc
376 * to estimate how long a request will take to complete.
377 *
378 * @param dram_pkt The request for which we want to estimate latency
379 * @param inTime The tick at which you want to probe the memory
380 *
381 * @return A pair of ticks, one indicating how many ticks *after*
382 * inTime the request require, and the other indicating how
383 * much of that was just the bank access time, ignoring the
384 * ticks spent simply waiting for resources to become free
385 */
386 std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime);
387
388 /**
389 * Move the request at the head of the read queue to the response
390 * queue, sorting by readyTime.\ If it is the only packet in the
391 * response queue, schedule a respond event to send it back to the
392 * outside world
393 */
394 void moveToRespQ();
395
396 /**
397 * For FR-FCFS policy reorder the read/write queue depending on row buffer
398 * hits and earliest banks available in DRAM
399 */
400 void reorderQueue(std::deque<DRAMPacket*>& queue);
401
402 /**
370 * Move the request at the head of the read queue to the response
371 * queue, sorting by readyTime.\ If it is the only packet in the
372 * response queue, schedule a respond event to send it back to the
373 * outside world
374 */
375 void moveToRespQ();
376
377 /**
378 * For FR-FCFS policy reorder the read/write queue depending on row buffer
379 * hits and earliest banks available in DRAM
380 */
381 void reorderQueue(std::deque<DRAMPacket*>& queue);
382
383 /**
403 * Find which are the earliest available banks for the enqueued
404 * requests. Assumes maximum of 64 banks per DIMM
384 * Find which are the earliest banks ready to issue an activate
385 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
405 *
406 * @param Queued requests to consider
407 * @return One-hot encoded mask of bank indices
408 */
386 *
387 * @param Queued requests to consider
388 * @return One-hot encoded mask of bank indices
389 */
409 uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const;
390 uint64_t minBankActAt(const std::deque<DRAMPacket*>& queue) const;
410
411 /**
412 * Keep track of when row activations happen, in order to enforce
413 * the maximum number of activations in the activation window. The
414 * method updates the time that the banks become available based
415 * on the current limits.
416 *
417 * @param act_tick Time when the activation takes place

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424 uint16_t row, Bank& bank_ref);
425
426 /**
427 * Precharge a given bank and also update when the precharge is
428 * done. This will also deal with any stats related to the
429 * accesses to the open page.
430 *
431 * @param bank The bank to precharge
391
392 /**
393 * Keep track of when row activations happen, in order to enforce
394 * the maximum number of activations in the activation window. The
395 * method updates the time that the banks become available based
396 * on the current limits.
397 *
398 * @param act_tick Time when the activation takes place

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405 uint16_t row, Bank& bank_ref);
406
407 /**
408 * Precharge a given bank and also update when the precharge is
409 * done. This will also deal with any stats related to the
410 * accesses to the open page.
411 *
412 * @param bank The bank to precharge
432 * @param pre_done_at Time when the precharge is done
413 * @param pre_at Time when the precharge takes place
433 */
414 */
434 void prechargeBank(Bank& bank, Tick pre_done_at);
415 void prechargeBank(Bank& bank, Tick pre_at);
435
436 void printParams() const;
437
438 /**
439 * Used for debugging to observe the contents of the queues.
440 */
441 void printQs() const;
442

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645 Stats::Histogram bytesPerActivate;
646 Stats::Histogram rdPerTurnAround;
647 Stats::Histogram wrPerTurnAround;
648
649 // Latencies summed over all requests
650 Stats::Scalar totQLat;
651 Stats::Scalar totMemAccLat;
652 Stats::Scalar totBusLat;
416
417 void printParams() const;
418
419 /**
420 * Used for debugging to observe the contents of the queues.
421 */
422 void printQs() const;
423

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626 Stats::Histogram bytesPerActivate;
627 Stats::Histogram rdPerTurnAround;
628 Stats::Histogram wrPerTurnAround;
629
630 // Latencies summed over all requests
631 Stats::Scalar totQLat;
632 Stats::Scalar totMemAccLat;
633 Stats::Scalar totBusLat;
653 Stats::Scalar totBankLat;
654
655 // Average latencies per request
656 Stats::Formula avgQLat;
634
635 // Average latencies per request
636 Stats::Formula avgQLat;
657 Stats::Formula avgBankLat;
658 Stats::Formula avgBusLat;
659 Stats::Formula avgMemAccLat;
660
661 // Average bandwidth
662 Stats::Formula avgRdBW;
663 Stats::Formula avgWrBW;
664 Stats::Formula avgRdBWSys;
665 Stats::Formula avgWrBWSys;

--- 55 unchanged lines hidden --- 		637 Stats::Formula avgBusLat;
638 Stats::Formula avgMemAccLat;
639
640 // Average bandwidth
641 Stats::Formula avgRdBW;
642 Stats::Formula avgWrBW;
643 Stats::Formula avgRdBWSys;
644 Stats::Formula avgWrBWSys;

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