dram_ctrl.hh (10208:c249f7660eb7) dram_ctrl.hh (10210:793e5ff26e0b)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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138 };
139
140 BusState busState;
141
142 /** List to keep track of activate ticks */
143 std::vector<std::deque<Tick>> actTicks;
144
145 /**
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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138 };
139
140 BusState busState;
141
142 /** List to keep track of activate ticks */
143 std::vector<std::deque<Tick>> actTicks;
144
145 /**
146 * A basic class to track the bank state indirectly via times
147 * "freeAt" and "tRASDoneAt" and what page is currently open. The
148 * bank also keeps track of how many bytes have been accessed in
149 * the open row since it was opened.
146 * A basic class to track the bank state, i.e. what row is
147 * currently open (if any), when is the bank free to accept a new
148 * command, when can it be precharged, and when can it be
149 * activated.
150 *
151 * The bank also keeps track of how many bytes have been accessed
152 * in the open row since it was opened.
150 */
151 class Bank
152 {
153
154 public:
155
156 static const uint32_t NO_ROW = -1;
157
158 uint32_t openRow;
159
160 Tick freeAt;
153 */
154 class Bank
155 {
156
157 public:
158
159 static const uint32_t NO_ROW = -1;
160
161 uint32_t openRow;
162
163 Tick freeAt;
161 Tick tRASDoneAt;
164 Tick preAllowedAt;
162 Tick actAllowedAt;
163
164 uint32_t rowAccesses;
165 uint32_t bytesAccessed;
166
167 Bank() :
165 Tick actAllowedAt;
166
167 uint32_t rowAccesses;
168 uint32_t bytesAccessed;
169
170 Bank() :
168 openRow(NO_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0),
171 openRow(NO_ROW), freeAt(0), preAllowedAt(0), actAllowedAt(0),
169 rowAccesses(0), bytesAccessed(0)
170 { }
171 };
172
173 /**
174 * A burst helper helps organize and manage a packet that is larger than
175 * the DRAM burst size. A system packet that is larger than the burst size
176 * is split into multiple DRAM packets and all those DRAM packets point to

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405 */
406 uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const;
407
408 /**
409 * Keep track of when row activations happen, in order to enforce
410 * the maximum number of activations in the activation window. The
411 * method updates the time that the banks become available based
412 * on the current limits.
172 rowAccesses(0), bytesAccessed(0)
173 { }
174 };
175
176 /**
177 * A burst helper helps organize and manage a packet that is larger than
178 * the DRAM burst size. A system packet that is larger than the burst size
179 * is split into multiple DRAM packets and all those DRAM packets point to

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408 */
409 uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const;
410
411 /**
412 * Keep track of when row activations happen, in order to enforce
413 * the maximum number of activations in the activation window. The
414 * method updates the time that the banks become available based
415 * on the current limits.
416 *
417 * @param act_tick Time when the activation takes place
418 * @param rank Index of the rank
419 * @param bank Index of the bank
420 * @param row Index of the row
421 * @param bank_ref Reference to the bank
413 */
422 */
414 void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank,
415 uint16_t row);
423 void activateBank(Tick act_tick, uint8_t rank, uint8_t bank,
424 uint16_t row, Bank& bank_ref);
416
417 /**
418 * Precharge a given bank and also update when the precharge is
419 * done. This will also deal with any stats related to the
420 * accesses to the open page.
421 *
422 * @param bank The bank to precharge
425
426 /**
427 * Precharge a given bank and also update when the precharge is
428 * done. This will also deal with any stats related to the
429 * accesses to the open page.
430 *
431 * @param bank The bank to precharge
423 * @param free_at Time when the precharge is done
432 * @param pre_done_at Time when the precharge is done
424 */
433 */
425 void prechargeBank(Bank& bank, Tick free_at);
434 void prechargeBank(Bank& bank, Tick pre_done_at);
426
427 void printParams() const;
428
429 /**
430 * Used for debugging to observe the contents of the queues.
431 */
432 void printQs() const;
433

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490 */
491 const Tick tWTR;
492 const Tick tRTW;
493 const Tick tBURST;
494 const Tick tRCD;
495 const Tick tCL;
496 const Tick tRP;
497 const Tick tRAS;
435
436 void printParams() const;
437
438 /**
439 * Used for debugging to observe the contents of the queues.
440 */
441 void printQs() const;
442

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499 */
500 const Tick tWTR;
501 const Tick tRTW;
502 const Tick tBURST;
503 const Tick tRCD;
504 const Tick tCL;
505 const Tick tRP;
506 const Tick tRAS;
507 const Tick tWR;
498 const Tick tRFC;
499 const Tick tREFI;
500 const Tick tRRD;
501 const Tick tXAW;
502 const uint32_t activationLimit;
503
504 /**
505 * Memory controller configuration initialized based on parameter

--- 205 unchanged lines hidden --- 		508 const Tick tRFC;
509 const Tick tREFI;
510 const Tick tRRD;
511 const Tick tXAW;
512 const uint32_t activationLimit;
513
514 /**
515 * Memory controller configuration initialized based on parameter

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