dram_ctrl.hh (10207:3112b31596f0) dram_ctrl.hh (10208:c249f7660eb7)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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255 };
256
257 /**
258 * Bunch of things requires to setup "events" in gem5
259 * When event "respondEvent" occurs for example, the method
260 * processRespondEvent is called; no parameters are allowed
261 * in these methods
262 */
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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255 };
256
257 /**
258 * Bunch of things requires to setup "events" in gem5
259 * When event "respondEvent" occurs for example, the method
260 * processRespondEvent is called; no parameters are allowed
261 * in these methods
262 */
263 void processNextReqEvent();
264 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
265
263 void processRespondEvent();
264 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
265
266 void processRespondEvent();
267 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
268
269 void processActivateEvent();
270 EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent;
271
272 void processPrechargeEvent();
273 EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent;
274
266 void processRefreshEvent();
267 EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
268
275 void processRefreshEvent();
276 EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
277
269 void processNextReqEvent();
270 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
278 void processPowerEvent();
279 EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent;
271
280
272
273 /**
274 * Check if the read queue has room for more entries
275 *
276 * @param pktCount The number of entries needed in the read queue
277 * @return true if read queue is full, false otherwise
278 */
279 bool readQueueFull(unsigned int pktCount) const;
280

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544 REF_IDLE = 0,
545 REF_DRAIN,
546 REF_PRE,
547 REF_RUN
548 };
549
550 RefreshState refreshState;
551
281 /**
282 * Check if the read queue has room for more entries
283 *
284 * @param pktCount The number of entries needed in the read queue
285 * @return true if read queue is full, false otherwise
286 */
287 bool readQueueFull(unsigned int pktCount) const;
288

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552 REF_IDLE = 0,
553 REF_DRAIN,
554 REF_PRE,
555 REF_RUN
556 };
557
558 RefreshState refreshState;
559
560 /**
561 * The power state captures the different operational states of
562 * the DRAM and interacts with the bus read/write state machine,
563 * and the refresh state machine. In the idle state all banks are
564 * precharged. From there we either go to an auto refresh (as
565 * determined by the refresh state machine), or to a precharge
566 * power down mode. From idle the memory can also go to the active
567 * state (with one or more banks active), and in turn from there
568 * to active power down. At the moment we do not capture the deep
569 * power down and self-refresh state.
570 */
571 enum PowerState {
572 PWR_IDLE = 0,
573 PWR_REF,
574 PWR_PRE_PDN,
575 PWR_ACT,
576 PWR_ACT_PDN
577 };
578
579 /**
580 * Since we are taking decisions out of order, we need to keep
581 * track of what power transition is happening at what time, such
582 * that we can go back in time and change history. For example, if
583 * we precharge all banks and schedule going to the idle state, we
584 * might at a later point decide to activate a bank before the
585 * transition to idle would have taken place.
586 */
587 PowerState pwrStateTrans;
588
589 /**
590 * Current power state.
591 */
592 PowerState pwrState;
593
594 /**
595 * Schedule a power state transition in the future, and
596 * potentially override an already scheduled transition.
597 *
598 * @param pwr_state Power state to transition to
599 * @param tick Tick when transition should take place
600 */
601 void schedulePowerEvent(PowerState pwr_state, Tick tick);
602
552 Tick prevArrival;
553
554 /**
555 * The soonest you have to start thinking about the next request
556 * is the longest access time that can occur before
557 * busBusyUntil. Assuming you need to precharge, open a new row,
558 * and access, it is tRP + tRCD + tCL.
559 */

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615 Stats::Scalar readRowHits;
616 Stats::Scalar writeRowHits;
617 Stats::Formula readRowHitRate;
618 Stats::Formula writeRowHitRate;
619 Stats::Formula avgGap;
620
621 // DRAM Power Calculation
622 Stats::Formula pageHitRate;
603 Tick prevArrival;
604
605 /**
606 * The soonest you have to start thinking about the next request
607 * is the longest access time that can occur before
608 * busBusyUntil. Assuming you need to precharge, open a new row,
609 * and access, it is tRP + tRCD + tCL.
610 */

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666 Stats::Scalar readRowHits;
667 Stats::Scalar writeRowHits;
668 Stats::Formula readRowHitRate;
669 Stats::Formula writeRowHitRate;
670 Stats::Formula avgGap;
671
672 // DRAM Power Calculation
673 Stats::Formula pageHitRate;
623 Stats::Formula prechargeAllPercent;
624 Stats::Scalar prechargeAllTime;
674 Stats::Vector pwrStateTime;
625
675
626 // To track number of cycles the DRAM is idle, i.e. all the banks
627 // are precharged
628 Tick idleStartTick;
676 // Track when we transitioned to the current power state
677 Tick pwrStateTick;
629
630 // To track number of banks which are currently active
631 unsigned int numBanksActive;
632
633 /** @todo this is a temporary workaround until the 4-phase code is
634 * committed. upstream caches needs this packet until true is returned, so
635 * hold onto it for deletion until a subsequent call
636 */

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679 // To track number of banks which are currently active
680 unsigned int numBanksActive;
681
682 /** @todo this is a temporary workaround until the 4-phase code is
683 * committed. upstream caches needs this packet until true is returned, so
684 * hold onto it for deletion until a subsequent call
685 */

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