dram_ctrl.hh (10206:823f7fd1a82f) dram_ctrl.hh (10207:3112b31596f0)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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148 * bank also keeps track of how many bytes have been accessed in
149 * the open row since it was opened.
150 */
151 class Bank
152 {
153
154 public:
155
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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148 * bank also keeps track of how many bytes have been accessed in
149 * the open row since it was opened.
150 */
151 class Bank
152 {
153
154 public:
155
156 static const uint32_t INVALID_ROW = -1;
156 static const uint32_t NO_ROW = -1;
157
158 uint32_t openRow;
159
160 Tick freeAt;
161 Tick tRASDoneAt;
162 Tick actAllowedAt;
163
164 uint32_t rowAccesses;
165 uint32_t bytesAccessed;
166
167 Bank() :
157
158 uint32_t openRow;
159
160 Tick freeAt;
161 Tick tRASDoneAt;
162 Tick actAllowedAt;
163
164 uint32_t rowAccesses;
165 uint32_t bytesAccessed;
166
167 Bank() :
168 openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0),
168 openRow(NO_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0),
169 rowAccesses(0), bytesAccessed(0)
170 { }
171 };
172
173 /**
174 * A burst helper helps organize and manage a packet that is larger than
175 * the DRAM burst size. A system packet that is larger than the burst size
176 * is split into multiple DRAM packets and all those DRAM packets point to

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384
385 /**
386 * For FR-FCFS policy reorder the read/write queue depending on row buffer
387 * hits and earliest banks available in DRAM
388 */
389 void reorderQueue(std::deque<DRAMPacket*>& queue);
390
391 /**
169 rowAccesses(0), bytesAccessed(0)
170 { }
171 };
172
173 /**
174 * A burst helper helps organize and manage a packet that is larger than
175 * the DRAM burst size. A system packet that is larger than the burst size
176 * is split into multiple DRAM packets and all those DRAM packets point to

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384
385 /**
386 * For FR-FCFS policy reorder the read/write queue depending on row buffer
387 * hits and earliest banks available in DRAM
388 */
389 void reorderQueue(std::deque<DRAMPacket*>& queue);
390
391 /**
392 * Looking at all banks, determine the moment in time when they
393 * are all free.
394 *
395 * @return The tick when all banks are free
396 */
397 Tick maxBankFreeAt() const;
398
399 /**
400 * Find which are the earliest available banks for the enqueued
401 * requests. Assumes maximum of 64 banks per DIMM
402 *
403 * @param Queued requests to consider
404 * @return One-hot encoded mask of bank indices
405 */
406 uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const;
407
408 /**
409 * Keep track of when row activations happen, in order to enforce
410 * the maximum number of activations in the activation window. The
411 * method updates the time that the banks become available based
412 * on the current limits.
413 */
392 * Find which are the earliest available banks for the enqueued
393 * requests. Assumes maximum of 64 banks per DIMM
394 *
395 * @param Queued requests to consider
396 * @return One-hot encoded mask of bank indices
397 */
398 uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const;
399
400 /**
401 * Keep track of when row activations happen, in order to enforce
402 * the maximum number of activations in the activation window. The
403 * method updates the time that the banks become available based
404 * on the current limits.
405 */
414 void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank);
406 void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank,
407 uint16_t row);
415
408
409 /**
410 * Precharge a given bank and also update when the precharge is
411 * done. This will also deal with any stats related to the
412 * accesses to the open page.
413 *
414 * @param bank The bank to precharge
415 * @param free_at Time when the precharge is done
416 */
417 void prechargeBank(Bank& bank, Tick free_at);
418
416 void printParams() const;
417
418 /**
419 * Used for debugging to observe the contents of the queues.
420 */
421 void printQs() const;
422
423 /**

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518 */
519 const Tick backendLatency;
520
521 /**
522 * Till when has the main data bus been spoken for already?
523 */
524 Tick busBusyUntil;
525
419 void printParams() const;
420
421 /**
422 * Used for debugging to observe the contents of the queues.
423 */
424 void printQs() const;
425
426 /**

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521 */
522 const Tick backendLatency;
523
524 /**
525 * Till when has the main data bus been spoken for already?
526 */
527 Tick busBusyUntil;
528
529 /**
530 * Keep track of when a refresh is due.
531 */
532 Tick refreshDueAt;
533
534 /**
535 * The refresh state is used to control the progress of the
536 * refresh scheduling. When normal operation is in progress the
537 * refresh state is idle. From there, it progresses to the refresh
538 * drain state once tREFI has passed. The refresh drain state
539 * captures the DRAM row active state, as it will stay there until
540 * all ongoing accesses complete. Thereafter all banks are
541 * precharged, and lastly, the DRAM is refreshed.
542 */
543 enum RefreshState {
544 REF_IDLE = 0,
545 REF_DRAIN,
546 REF_PRE,
547 REF_RUN
548 };
549
550 RefreshState refreshState;
551
526 Tick prevArrival;
527
528 /**
529 * The soonest you have to start thinking about the next request
530 * is the longest access time that can occur before
531 * busBusyUntil. Assuming you need to precharge, open a new row,
532 * and access, it is tRP + tRCD + tCL.
533 */

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592 Stats::Formula writeRowHitRate;
593 Stats::Formula avgGap;
594
595 // DRAM Power Calculation
596 Stats::Formula pageHitRate;
597 Stats::Formula prechargeAllPercent;
598 Stats::Scalar prechargeAllTime;
599
552 Tick prevArrival;
553
554 /**
555 * The soonest you have to start thinking about the next request
556 * is the longest access time that can occur before
557 * busBusyUntil. Assuming you need to precharge, open a new row,
558 * and access, it is tRP + tRCD + tCL.
559 */

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618 Stats::Formula writeRowHitRate;
619 Stats::Formula avgGap;
620
621 // DRAM Power Calculation
622 Stats::Formula pageHitRate;
623 Stats::Formula prechargeAllPercent;
624 Stats::Scalar prechargeAllTime;
625
600 // To track number of cycles all the banks are precharged
601 Tick startTickPrechargeAll;
626 // To track number of cycles the DRAM is idle, i.e. all the banks
627 // are precharged
628 Tick idleStartTick;
629
602 // To track number of banks which are currently active
603 unsigned int numBanksActive;
604
605 /** @todo this is a temporary workaround until the 4-phase code is
606 * committed. upstream caches needs this packet until true is returned, so
607 * hold onto it for deletion until a subsequent call
608 */
609 std::vector<PacketPtr> pendingDelete;

--- 24 unchanged lines hidden --- 		630 // To track number of banks which are currently active
631 unsigned int numBanksActive;
632
633 /** @todo this is a temporary workaround until the 4-phase code is
634 * committed. upstream caches needs this packet until true is returned, so
635 * hold onto it for deletion until a subsequent call
636 */
637 std::vector<PacketPtr> pendingDelete;

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