1/*
2 * Copyright (c) 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 */
46
47/**
48 * @file
49 * DRAMCtrl declaration
50 */
51
52#ifndef __MEM_DRAM_CTRL_HH__
53#define __MEM_DRAM_CTRL_HH__
54
55#include <deque>
56#include <string>
57#include <unordered_set>
58
59#include "base/statistics.hh"
60#include "enums/AddrMap.hh"
61#include "enums/MemSched.hh"
62#include "enums/PageManage.hh"
63#include "mem/abstract_mem.hh"
64#include "mem/qport.hh"
65#include "params/DRAMCtrl.hh"
66#include "sim/eventq.hh"
67#include "mem/drampower.hh"
68
69/**
70 * The DRAM controller is a single-channel memory controller capturing
71 * the most important timing constraints associated with a
72 * contemporary DRAM. For multi-channel memory systems, the controller
73 * is combined with a crossbar model, with the channel address
74 * interleaving taking part in the crossbar.
75 *
76 * As a basic design principle, this controller
77 * model is not cycle callable, but instead uses events to: 1) decide
78 * when new decisions can be made, 2) when resources become available,
79 * 3) when things are to be considered done, and 4) when to send
80 * things back. Through these simple principles, the model delivers
81 * high performance, and lots of flexibility, allowing users to
82 * evaluate the system impact of a wide range of memory technologies,
83 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
84 *
85 * For more details, please see Hansson et al, "Simulating DRAM
86 * controllers for future system architecture exploration",
87 * Proc. ISPASS, 2014. If you use this model as part of your research
88 * please cite the paper.
89 */
90class DRAMCtrl : public AbstractMemory
91{
92
93 private:
94
95 // For now, make use of a queued slave port to avoid dealing with
96 // flow control for the responses being sent back
97 class MemoryPort : public QueuedSlavePort
98 {
99
100 RespPacketQueue queue;
101 DRAMCtrl& memory;
102
103 public:
104
105 MemoryPort(const std::string& name, DRAMCtrl& _memory);
106
107 protected:
108
109 Tick recvAtomic(PacketPtr pkt);
110
111 void recvFunctional(PacketPtr pkt);
112
113 bool recvTimingReq(PacketPtr);
114
115 virtual AddrRangeList getAddrRanges() const;
116
117 };
118
119 /**
120 * Our incoming port, for a multi-ported controller add a crossbar
121 * in front of it
122 */
123 MemoryPort port;
124
125 /**
126 * Remeber if the memory system is in timing mode
127 */
128 bool isTimingMode;
129
130 /**
131 * Remember if we have to retry a request when available.
132 */
133 bool retryRdReq;
134 bool retryWrReq;
135
136 /**
137 * Bus state used to control the read/write switching and drive
138 * the scheduling of the next request.
139 */
140 enum BusState {
141 READ = 0,
142 READ_TO_WRITE,
143 WRITE,
144 WRITE_TO_READ
145 };
146
147 BusState busState;
148
149 /**
150 * Simple structure to hold the values needed to keep track of
151 * commands for DRAMPower
152 */
153 struct Command {
154 Data::MemCommand::cmds type;
155 uint8_t bank;
156 Tick timeStamp;
157
158 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
159 Tick time_stamp)
160 : type(_type), bank(_bank), timeStamp(time_stamp)
161 { }
162 };
163
164 /**
165 * A basic class to track the bank state, i.e. what row is
166 * currently open (if any), when is the bank free to accept a new
167 * column (read/write) command, when can it be precharged, and
168 * when can it be activated.
169 *
170 * The bank also keeps track of how many bytes have been accessed
171 * in the open row since it was opened.
172 */
173 class Bank
174 {
175
176 public:
177
178 static const uint32_t NO_ROW = -1;
179
180 uint32_t openRow;
181 uint8_t bank;
182 uint8_t bankgr;
183
184 Tick colAllowedAt;
185 Tick preAllowedAt;
186 Tick actAllowedAt;
187
188 uint32_t rowAccesses;
189 uint32_t bytesAccessed;
190
191 Bank() :
192 openRow(NO_ROW), bank(0), bankgr(0),
193 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
194 rowAccesses(0), bytesAccessed(0)
195 { }
196 };
197
198
199 /**
200 * Rank class includes a vector of banks. Refresh and Power state
201 * machines are defined per rank. Events required to change the
202 * state of the refresh and power state machine are scheduled per
203 * rank. This class allows the implementation of rank-wise refresh
204 * and rank-wise power-down.
205 */
206 class Rank : public EventManager
207 {
208
209 private:
210
211 /**
212 * The power state captures the different operational states of
213 * the DRAM and interacts with the bus read/write state machine,
214 * and the refresh state machine. In the idle state all banks are
215 * precharged. From there we either go to an auto refresh (as
216 * determined by the refresh state machine), or to a precharge
217 * power down mode. From idle the memory can also go to the active
218 * state (with one or more banks active), and in turn from there
219 * to active power down. At the moment we do not capture the deep
220 * power down and self-refresh state.
221 */
222 enum PowerState {
223 PWR_IDLE = 0,
224 PWR_REF,
225 PWR_PRE_PDN,
226 PWR_ACT,
227 PWR_ACT_PDN
228 };
229
230 /**
231 * The refresh state is used to control the progress of the
232 * refresh scheduling. When normal operation is in progress the
233 * refresh state is idle. From there, it progresses to the refresh
234 * drain state once tREFI has passed. The refresh drain state
235 * captures the DRAM row active state, as it will stay there until
236 * all ongoing accesses complete. Thereafter all banks are
237 * precharged, and lastly, the DRAM is refreshed.
238 */
239 enum RefreshState {
240 REF_IDLE = 0,
241 REF_DRAIN,
242 REF_PRE,
243 REF_RUN
244 };
245
246 /**
247 * A reference to the parent DRAMCtrl instance
248 */
249 DRAMCtrl& memory;
250
251 /**
252 * Since we are taking decisions out of order, we need to keep
253 * track of what power transition is happening at what time, such
254 * that we can go back in time and change history. For example, if
255 * we precharge all banks and schedule going to the idle state, we
256 * might at a later point decide to activate a bank before the
257 * transition to idle would have taken place.
258 */
259 PowerState pwrStateTrans;
260
261 /**
262 * Current power state.
263 */
264 PowerState pwrState;
265
266 /**
267 * Track when we transitioned to the current power state
268 */
269 Tick pwrStateTick;
270
271 /**
272 * current refresh state
273 */
274 RefreshState refreshState;
275
276 /**
277 * Keep track of when a refresh is due.
278 */
279 Tick refreshDueAt;
280
281 /*
282 * Command energies
283 */
284 Stats::Scalar actEnergy;
285 Stats::Scalar preEnergy;
286 Stats::Scalar readEnergy;
287 Stats::Scalar writeEnergy;
288 Stats::Scalar refreshEnergy;
289
290 /*
291 * Active Background Energy
292 */
293 Stats::Scalar actBackEnergy;
294
295 /*
296 * Precharge Background Energy
297 */
298 Stats::Scalar preBackEnergy;
299
300 Stats::Scalar totalEnergy;
301 Stats::Scalar averagePower;
302
303 /**
304 * Track time spent in each power state.
305 */
306 Stats::Vector pwrStateTime;
307
308 /**
309 * Function to update Power Stats
310 */
311 void updatePowerStats();
312
313 /**
314 * Schedule a power state transition in the future, and
315 * potentially override an already scheduled transition.
316 *
317 * @param pwr_state Power state to transition to
318 * @param tick Tick when transition should take place
319 */
320 void schedulePowerEvent(PowerState pwr_state, Tick tick);
321
322 public:
323
324 /**
325 * Current Rank index
326 */
327 uint8_t rank;
328
329 /**
330 * One DRAMPower instance per rank
331 */
332 DRAMPower power;
333
334 /**
335 * List of comamnds issued, to be sent to DRAMPpower at refresh
336 * and stats dump. Keep commands here since commands to different
337 * banks are added out of order. Will only pass commands up to
338 * curTick() to DRAMPower after sorting.
339 */
340 std::vector<Command> cmdList;
341
342 /**
343 * Vector of Banks. Each rank is made of several devices which in
344 * term are made from several banks.
345 */
346 std::vector<Bank> banks;
347
348 /**
349 * To track number of banks which are currently active for
350 * this rank.
351 */
352 unsigned int numBanksActive;
353
354 /** List to keep track of activate ticks */
355 std::deque<Tick> actTicks;
356
357 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p);
358
359 const std::string name() const
360 {
361 return csprintf("%s_%d", memory.name(), rank);
362 }
363
364 /**
365 * Kick off accounting for power and refresh states and
366 * schedule initial refresh.
367 *
368 * @param ref_tick Tick for first refresh
369 */
370 void startup(Tick ref_tick);
371
372 /**
373 * Stop the refresh events.
374 */
375 void suspend();
376
377 /**
378 * Check if the current rank is available for scheduling.
379 *
380 * @param Return true if the rank is idle from a refresh point of view
381 */
382 bool isAvailable() const { return refreshState == REF_IDLE; }
383
384 /**
|
385 * Check if the current rank has all banks closed and is not
386 * in a low power state
387 *
388 * @param Return true if the rank is idle from a bank
389 * and power point of view
390 */
391 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
392
393 /** |
394 * Let the rank check if it was waiting for requests to drain
395 * to allow it to transition states.
396 */
397 void checkDrainDone();
398
399 /**
400 * Push command out of cmdList queue that are scheduled at
401 * or before curTick() to DRAMPower library
402 * All commands before curTick are guaranteed to be complete
403 * and can safely be flushed.
404 */
405 void flushCmdList();
406
407 /*
408 * Function to register Stats
409 */
410 void regStats();
411
412 void processActivateEvent();
413 EventWrapper<Rank, &Rank::processActivateEvent>
414 activateEvent;
415
416 void processPrechargeEvent();
417 EventWrapper<Rank, &Rank::processPrechargeEvent>
418 prechargeEvent;
419
420 void processRefreshEvent();
421 EventWrapper<Rank, &Rank::processRefreshEvent>
422 refreshEvent;
423
424 void processPowerEvent();
425 EventWrapper<Rank, &Rank::processPowerEvent>
426 powerEvent;
427
428 };
429
430 /**
431 * A burst helper helps organize and manage a packet that is larger than
432 * the DRAM burst size. A system packet that is larger than the burst size
433 * is split into multiple DRAM packets and all those DRAM packets point to
434 * a single burst helper such that we know when the whole packet is served.
435 */
436 class BurstHelper {
437
438 public:
439
440 /** Number of DRAM bursts requred for a system packet **/
441 const unsigned int burstCount;
442
443 /** Number of DRAM bursts serviced so far for a system packet **/
444 unsigned int burstsServiced;
445
446 BurstHelper(unsigned int _burstCount)
447 : burstCount(_burstCount), burstsServiced(0)
448 { }
449 };
450
451 /**
452 * A DRAM packet stores packets along with the timestamp of when
453 * the packet entered the queue, and also the decoded address.
454 */
455 class DRAMPacket {
456
457 public:
458
459 /** When did request enter the controller */
460 const Tick entryTime;
461
462 /** When will request leave the controller */
463 Tick readyTime;
464
465 /** This comes from the outside world */
466 const PacketPtr pkt;
467
468 const bool isRead;
469
470 /** Will be populated by address decoder */
471 const uint8_t rank;
472 const uint8_t bank;
473 const uint32_t row;
474
475 /**
476 * Bank id is calculated considering banks in all the ranks
477 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
478 * bankId = 8 --> rank1, bank0
479 */
480 const uint16_t bankId;
481
482 /**
483 * The starting address of the DRAM packet.
484 * This address could be unaligned to burst size boundaries. The
485 * reason is to keep the address offset so we can accurately check
486 * incoming read packets with packets in the write queue.
487 */
488 Addr addr;
489
490 /**
491 * The size of this dram packet in bytes
492 * It is always equal or smaller than DRAM burst size
493 */
494 unsigned int size;
495
496 /**
497 * A pointer to the BurstHelper if this DRAMPacket is a split packet
498 * If not a split packet (common case), this is set to NULL
499 */
500 BurstHelper* burstHelper;
501 Bank& bankRef;
502 Rank& rankRef;
503
504 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
505 uint32_t _row, uint16_t bank_id, Addr _addr,
506 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
507 : entryTime(curTick()), readyTime(curTick()),
508 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
509 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
510 bankRef(bank_ref), rankRef(rank_ref)
511 { }
512
513 };
514
515 /**
516 * Bunch of things requires to setup "events" in gem5
517 * When event "respondEvent" occurs for example, the method
518 * processRespondEvent is called; no parameters are allowed
519 * in these methods
520 */
521 void processNextReqEvent();
522 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
523
524 void processRespondEvent();
525 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
526
527 /**
528 * Check if the read queue has room for more entries
529 *
530 * @param pktCount The number of entries needed in the read queue
531 * @return true if read queue is full, false otherwise
532 */
533 bool readQueueFull(unsigned int pktCount) const;
534
535 /**
536 * Check if the write queue has room for more entries
537 *
538 * @param pktCount The number of entries needed in the write queue
539 * @return true if write queue is full, false otherwise
540 */
541 bool writeQueueFull(unsigned int pktCount) const;
542
543 /**
544 * When a new read comes in, first check if the write q has a
545 * pending request to the same address.\ If not, decode the
546 * address to populate rank/bank/row, create one or mutliple
547 * "dram_pkt", and push them to the back of the read queue.\
548 * If this is the only
549 * read request in the system, schedule an event to start
550 * servicing it.
551 *
552 * @param pkt The request packet from the outside world
553 * @param pktCount The number of DRAM bursts the pkt
554 * translate to. If pkt size is larger then one full burst,
555 * then pktCount is greater than one.
556 */
557 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
558
559 /**
560 * Decode the incoming pkt, create a dram_pkt and push to the
561 * back of the write queue. \If the write q length is more than
562 * the threshold specified by the user, ie the queue is beginning
563 * to get full, stop reads, and start draining writes.
564 *
565 * @param pkt The request packet from the outside world
566 * @param pktCount The number of DRAM bursts the pkt
567 * translate to. If pkt size is larger then one full burst,
568 * then pktCount is greater than one.
569 */
570 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
571
572 /**
573 * Actually do the DRAM access - figure out the latency it
574 * will take to service the req based on bank state, channel state etc
575 * and then update those states to account for this request.\ Based
576 * on this, update the packet's "readyTime" and move it to the
577 * response q from where it will eventually go back to the outside
578 * world.
579 *
580 * @param pkt The DRAM packet created from the outside world pkt
581 */
582 void doDRAMAccess(DRAMPacket* dram_pkt);
583
584 /**
585 * When a packet reaches its "readyTime" in the response Q,
586 * use the "access()" method in AbstractMemory to actually
587 * create the response packet, and send it back to the outside
588 * world requestor.
589 *
590 * @param pkt The packet from the outside world
591 * @param static_latency Static latency to add before sending the packet
592 */
593 void accessAndRespond(PacketPtr pkt, Tick static_latency);
594
595 /**
596 * Address decoder to figure out physical mapping onto ranks,
597 * banks, and rows. This function is called multiple times on the same
598 * system packet if the pakcet is larger than burst of the memory. The
599 * dramPktAddr is used for the offset within the packet.
600 *
601 * @param pkt The packet from the outside world
602 * @param dramPktAddr The starting address of the DRAM packet
603 * @param size The size of the DRAM packet in bytes
604 * @param isRead Is the request for a read or a write to DRAM
605 * @return A DRAMPacket pointer with the decoded information
606 */
607 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
608 bool isRead);
609
610 /**
611 * The memory schduler/arbiter - picks which request needs to
612 * go next, based on the specified policy such as FCFS or FR-FCFS
613 * and moves it to the head of the queue.
614 * Prioritizes accesses to the same rank as previous burst unless
615 * controller is switching command type.
616 *
617 * @param queue Queued requests to consider
618 * @param extra_col_delay Any extra delay due to a read/write switch
619 * @return true if a packet is scheduled to a rank which is available else
620 * false
621 */
622 bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
623
624 /**
625 * For FR-FCFS policy reorder the read/write queue depending on row buffer
626 * hits and earliest bursts available in DRAM
627 *
628 * @param queue Queued requests to consider
629 * @param extra_col_delay Any extra delay due to a read/write switch
630 * @return true if a packet is scheduled to a rank which is available else
631 * false
632 */
633 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
634
635 /**
636 * Find which are the earliest banks ready to issue an activate
637 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
638 * Also checks if the bank is already prepped.
639 *
640 * @param queue Queued requests to consider
641 * @param time of seamless burst command
642 * @return One-hot encoded mask of bank indices
643 * @return boolean indicating burst can issue seamlessly, with no gaps
644 */
645 std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue,
646 Tick min_col_at) const;
647
648 /**
649 * Keep track of when row activations happen, in order to enforce
650 * the maximum number of activations in the activation window. The
651 * method updates the time that the banks become available based
652 * on the current limits.
653 *
654 * @param rank_ref Reference to the rank
655 * @param bank_ref Reference to the bank
656 * @param act_tick Time when the activation takes place
657 * @param row Index of the row
658 */
659 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
660 uint32_t row);
661
662 /**
663 * Precharge a given bank and also update when the precharge is
664 * done. This will also deal with any stats related to the
665 * accesses to the open page.
666 *
667 * @param rank_ref The rank to precharge
668 * @param bank_ref The bank to precharge
669 * @param pre_at Time when the precharge takes place
670 * @param trace Is this an auto precharge then do not add to trace
671 */
672 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
673 Tick pre_at, bool trace = true);
674
675 /**
676 * Used for debugging to observe the contents of the queues.
677 */
678 void printQs() const;
679
680 /**
681 * Burst-align an address.
682 *
683 * @param addr The potentially unaligned address
684 *
685 * @return An address aligned to a DRAM burst
686 */
687 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
688
689 /**
690 * The controller's main read and write queues
691 */
692 std::deque<DRAMPacket*> readQueue;
693 std::deque<DRAMPacket*> writeQueue;
694
695 /**
696 * To avoid iterating over the write queue to check for
697 * overlapping transactions, maintain a set of burst addresses
698 * that are currently queued. Since we merge writes to the same
699 * location we never have more than one address to the same burst
700 * address.
701 */
702 std::unordered_set<Addr> isInWriteQueue;
703
704 /**
705 * Response queue where read packets wait after we're done working
706 * with them, but it's not time to send the response yet. The
707 * responses are stored seperately mostly to keep the code clean
708 * and help with events scheduling. For all logical purposes such
709 * as sizing the read queue, this and the main read queue need to
710 * be added together.
711 */
712 std::deque<DRAMPacket*> respQueue;
713
714 /**
715 * Vector of ranks
716 */
717 std::vector<Rank*> ranks;
718
719 /**
720 * The following are basic design parameters of the memory
721 * controller, and are initialized based on parameter values.
722 * The rowsPerBank is determined based on the capacity, number of
723 * ranks and banks, the burst size, and the row buffer size.
724 */
725 const uint32_t deviceSize;
726 const uint32_t deviceBusWidth;
727 const uint32_t burstLength;
728 const uint32_t deviceRowBufferSize;
729 const uint32_t devicesPerRank;
730 const uint32_t burstSize;
731 const uint32_t rowBufferSize;
732 const uint32_t columnsPerRowBuffer;
733 const uint32_t columnsPerStripe;
734 const uint32_t ranksPerChannel;
735 const uint32_t bankGroupsPerRank;
736 const bool bankGroupArch;
737 const uint32_t banksPerRank;
738 const uint32_t channels;
739 uint32_t rowsPerBank;
740 const uint32_t readBufferSize;
741 const uint32_t writeBufferSize;
742 const uint32_t writeHighThreshold;
743 const uint32_t writeLowThreshold;
744 const uint32_t minWritesPerSwitch;
745 uint32_t writesThisTime;
746 uint32_t readsThisTime;
747
748 /**
749 * Basic memory timing parameters initialized based on parameter
750 * values.
751 */
752 const Tick M5_CLASS_VAR_USED tCK;
753 const Tick tWTR;
754 const Tick tRTW;
755 const Tick tCS;
756 const Tick tBURST;
757 const Tick tCCD_L;
758 const Tick tRCD;
759 const Tick tCL;
760 const Tick tRP;
761 const Tick tRAS;
762 const Tick tWR;
763 const Tick tRTP;
764 const Tick tRFC;
765 const Tick tREFI;
766 const Tick tRRD;
767 const Tick tRRD_L;
768 const Tick tXAW;
769 const Tick tXP;
770 const Tick tXS;
771 const uint32_t activationLimit;
772
773 /**
774 * Memory controller configuration initialized based on parameter
775 * values.
776 */
777 Enums::MemSched memSchedPolicy;
778 Enums::AddrMap addrMapping;
779 Enums::PageManage pageMgmt;
780
781 /**
782 * Max column accesses (read and write) per row, before forefully
783 * closing it.
784 */
785 const uint32_t maxAccessesPerRow;
786
787 /**
788 * Pipeline latency of the controller frontend. The frontend
789 * contribution is added to writes (that complete when they are in
790 * the write buffer) and reads that are serviced the write buffer.
791 */
792 const Tick frontendLatency;
793
794 /**
795 * Pipeline latency of the backend and PHY. Along with the
796 * frontend contribution, this latency is added to reads serviced
797 * by the DRAM.
798 */
799 const Tick backendLatency;
800
801 /**
802 * Till when has the main data bus been spoken for already?
803 */
804 Tick busBusyUntil;
805
806 Tick prevArrival;
807
808 /**
809 * The soonest you have to start thinking about the next request
810 * is the longest access time that can occur before
811 * busBusyUntil. Assuming you need to precharge, open a new row,
812 * and access, it is tRP + tRCD + tCL.
813 */
814 Tick nextReqTime;
815
816 // All statistics that the model needs to capture
817 Stats::Scalar readReqs;
818 Stats::Scalar writeReqs;
819 Stats::Scalar readBursts;
820 Stats::Scalar writeBursts;
821 Stats::Scalar bytesReadDRAM;
822 Stats::Scalar bytesReadWrQ;
823 Stats::Scalar bytesWritten;
824 Stats::Scalar bytesReadSys;
825 Stats::Scalar bytesWrittenSys;
826 Stats::Scalar servicedByWrQ;
827 Stats::Scalar mergedWrBursts;
828 Stats::Scalar neitherReadNorWrite;
829 Stats::Vector perBankRdBursts;
830 Stats::Vector perBankWrBursts;
831 Stats::Scalar numRdRetry;
832 Stats::Scalar numWrRetry;
833 Stats::Scalar totGap;
834 Stats::Vector readPktSize;
835 Stats::Vector writePktSize;
836 Stats::Vector rdQLenPdf;
837 Stats::Vector wrQLenPdf;
838 Stats::Histogram bytesPerActivate;
839 Stats::Histogram rdPerTurnAround;
840 Stats::Histogram wrPerTurnAround;
841
842 // Latencies summed over all requests
843 Stats::Scalar totQLat;
844 Stats::Scalar totMemAccLat;
845 Stats::Scalar totBusLat;
846
847 // Average latencies per request
848 Stats::Formula avgQLat;
849 Stats::Formula avgBusLat;
850 Stats::Formula avgMemAccLat;
851
852 // Average bandwidth
853 Stats::Formula avgRdBW;
854 Stats::Formula avgWrBW;
855 Stats::Formula avgRdBWSys;
856 Stats::Formula avgWrBWSys;
857 Stats::Formula peakBW;
858 Stats::Formula busUtil;
859 Stats::Formula busUtilRead;
860 Stats::Formula busUtilWrite;
861
862 // Average queue lengths
863 Stats::Average avgRdQLen;
864 Stats::Average avgWrQLen;
865
866 // Row hit count and rate
867 Stats::Scalar readRowHits;
868 Stats::Scalar writeRowHits;
869 Stats::Formula readRowHitRate;
870 Stats::Formula writeRowHitRate;
871 Stats::Formula avgGap;
872
873 // DRAM Power Calculation
874 Stats::Formula pageHitRate;
875
876 // Holds the value of the rank of burst issued
877 uint8_t activeRank;
878
879 // timestamp offset
880 uint64_t timeStampOffset;
881
882 /**
883 * Upstream caches need this packet until true is returned, so
884 * hold it for deletion until a subsequent call
885 */
886 std::unique_ptr<Packet> pendingDelete;
887
888 /**
889 * This function increments the energy when called. If stats are
890 * dumped periodically, note accumulated energy values will
891 * appear in the stats (even if the stats are reset). This is a
892 * result of the energy values coming from DRAMPower, and there
893 * is currently no support for resetting the state.
894 *
895 * @param rank Currrent rank
896 */
897 void updatePowerStats(Rank& rank_ref);
898
899 /**
900 * Function for sorting Command structures based on timeStamp
901 *
902 * @param a Memory Command
903 * @param next Memory Command
904 * @return true if timeStamp of Command 1 < timeStamp of Command 2
905 */
906 static bool sortTime(const Command& cmd, const Command& cmd_next) {
907 return cmd.timeStamp < cmd_next.timeStamp;
908 };
909
910 public:
911
912 void regStats() override;
913
914 DRAMCtrl(const DRAMCtrlParams* p);
915
916 DrainState drain() override;
917
918 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
919 PortID idx = InvalidPortID) override;
920
921 virtual void init() override;
922 virtual void startup() override;
923 virtual void drainResume() override;
924
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925 /**
926 * Return true once refresh is complete for all ranks and there are no
927 * additional commands enqueued. (only evaluated when draining)
928 * This will ensure that all banks are closed, power state is IDLE, and
929 * power stats have been updated
930 *
931 * @return true if all ranks have refreshed, with no commands enqueued
932 *
933 */
934 bool allRanksDrained() const;
935 |
936 protected:
937
938 Tick recvAtomic(PacketPtr pkt);
939 void recvFunctional(PacketPtr pkt);
940 bool recvTimingReq(PacketPtr pkt);
941
942};
943
944#endif //__MEM_DRAM_CTRL_HH__
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