59a60
> #include <vector>
66c67,68
< #include "mem/abstract_mem.hh"
---
> #include "mem/drampower.hh"
> #include "mem/qos/mem_ctrl.hh"
70d71
< #include "mem/drampower.hh"
97c98
< class DRAMCtrl : public AbstractMemory
---
> class DRAMCtrl : public QoS::MemCtrl
133c134
< * Remeber if the memory system is in timing mode
---
> * Remember if the memory system is in timing mode
143,150c144
< /**
< * Bus state used to control the read/write switching and drive
< * the scheduling of the next request.
< */
< enum BusState {
< READ = 0,
< WRITE,
< };
---
> /**/
152,156d145
< BusState busState;
<
< /* bus state for next request event triggered */
< BusState busStateNext;
<
434c423
< * List of comamnds issued, to be sent to DRAMPpower at refresh
---
> * List of commands issued, to be sent to DRAMPpower at refresh
658c647,648
< const bool isRead;
---
> /** MasterID associated with the packet */
> const MasterID _masterId;
659a650,651
> const bool read;
>
693a686,733
> /**
> * QoS value of the encapsulated packet read at queuing time
> */
> uint8_t _qosValue;
>
> /**
> * Set the packet QoS value
> * (interface compatibility with Packet)
> */
> inline void qosValue(const uint8_t qv) { _qosValue = qv; }
>
> /**
> * Get the packet QoS value
> * (interface compatibility with Packet)
> */
> inline uint8_t qosValue() const { return _qosValue; }
>
> /**
> * Get the packet MasterID
> * (interface compatibility with Packet)
> */
> inline MasterID masterId() const { return _masterId; }
>
> /**
> * Get the packet size
> * (interface compatibility with Packet)
> */
> inline unsigned int getSize() const { return size; }
>
> /**
> * Get the packet address
> * (interface compatibility with Packet)
> */
> inline Addr getAddr() const { return addr; }
>
> /**
> * Return true if its a read packet
> * (interface compatibility with Packet)
> */
> inline bool isRead() const { return read; }
>
> /**
> * Return true if its a write packet
> * (interface compatibility with Packet)
> */
> inline bool isWrite() const { return !read; }
>
>
697,698c737,739
< : entryTime(curTick()), readyTime(curTick()),
< pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
---
> : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
> _masterId(pkt->masterId()),
> read(is_read), rank(_rank), bank(_bank), row(_row),
700c741
< bankRef(bank_ref), rankRef(rank_ref)
---
> bankRef(bank_ref), rankRef(rank_ref), _qosValue(_pkt->qosValue())
704a746,749
> // The DRAM packets are store in a multiple dequeue structure,
> // based on their QoS priority
> typedef std::deque<DRAMPacket*> DRAMPacketQueue;
>
809,810c854
< * @return true if a packet is scheduled to a rank which is available else
< * false
---
> * @return an iterator to the selected packet, else queue.end()
812c856,857
< bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
---
> DRAMPacketQueue::iterator chooseNext(DRAMPacketQueue& queue,
> Tick extra_col_delay);
820,821c865
< * @return true if a packet is scheduled to a rank which is available else
< * false
---
> * @return an iterator to the selected packet, else queue.end()
823c867,868
< bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
---
> DRAMPacketQueue::iterator chooseNextFRFCFS(DRAMPacketQueue& queue,
> Tick extra_col_delay);
835,837c880,881
< std::pair<std::vector<uint32_t>, bool> minBankPrep(
< const std::deque<DRAMPacket*>& queue,
< Tick min_col_at) const;
---
> std::pair<std::vector<uint32_t>, bool>
> minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const;
881c925
< * The controller's main read and write queues
---
> * The controller's main read and write queues, with support for QoS reordering
883,884c927,928
< std::deque<DRAMPacket*> readQueue;
< std::deque<DRAMPacket*> writeQueue;
---
> std::vector<DRAMPacketQueue> readQueue;
> std::vector<DRAMPacketQueue> writeQueue;
898c942
< * responses are stored seperately mostly to keep the code clean
---
> * responses are stored separately mostly to keep the code clean
976c1020
< * Max column accesses (read and write) per row, before forefully
---
> * Max column accesses (read and write) per row, before forcefully
1035a1080,1099
> // per-master bytes read and written to memory
> Stats::Vector masterReadBytes;
> Stats::Vector masterWriteBytes;
>
> // per-master bytes read and written to memory rate
> Stats::Formula masterReadRate;
> Stats::Formula masterWriteRate;
>
> // per-master read and write serviced memory accesses
> Stats::Vector masterReadAccesses;
> Stats::Vector masterWriteAccesses;
>
> // per-master read and write total memory access latency
> Stats::Vector masterReadTotalLat;
> Stats::Vector masterWriteTotalLat;
>
> // per-master raed and write average memory access latency
> Stats::Formula masterReadAvgLat;
> Stats::Formula masterWriteAvgLat;
>
1092c1156
< * @param rank Currrent rank
---
> * @param rank Current rank
> #include <vector>
66c67,68
< #include "mem/abstract_mem.hh"
---
> #include "mem/drampower.hh"
> #include "mem/qos/mem_ctrl.hh"
70d71
< #include "mem/drampower.hh"
97c98
< class DRAMCtrl : public AbstractMemory
---
> class DRAMCtrl : public QoS::MemCtrl
133c134
< * Remeber if the memory system is in timing mode
---
> * Remember if the memory system is in timing mode
143,150c144
< /**
< * Bus state used to control the read/write switching and drive
< * the scheduling of the next request.
< */
< enum BusState {
< READ = 0,
< WRITE,
< };
---
> /**/
152,156d145
< BusState busState;
<
< /* bus state for next request event triggered */
< BusState busStateNext;
<
434c423
< * List of comamnds issued, to be sent to DRAMPpower at refresh
---
> * List of commands issued, to be sent to DRAMPpower at refresh
658c647,648
< const bool isRead;
---
> /** MasterID associated with the packet */
> const MasterID _masterId;
659a650,651
> const bool read;
>
693a686,733
> /**
> * QoS value of the encapsulated packet read at queuing time
> */
> uint8_t _qosValue;
>
> /**
> * Set the packet QoS value
> * (interface compatibility with Packet)
> */
> inline void qosValue(const uint8_t qv) { _qosValue = qv; }
>
> /**
> * Get the packet QoS value
> * (interface compatibility with Packet)
> */
> inline uint8_t qosValue() const { return _qosValue; }
>
> /**
> * Get the packet MasterID
> * (interface compatibility with Packet)
> */
> inline MasterID masterId() const { return _masterId; }
>
> /**
> * Get the packet size
> * (interface compatibility with Packet)
> */
> inline unsigned int getSize() const { return size; }
>
> /**
> * Get the packet address
> * (interface compatibility with Packet)
> */
> inline Addr getAddr() const { return addr; }
>
> /**
> * Return true if its a read packet
> * (interface compatibility with Packet)
> */
> inline bool isRead() const { return read; }
>
> /**
> * Return true if its a write packet
> * (interface compatibility with Packet)
> */
> inline bool isWrite() const { return !read; }
>
>
697,698c737,739
< : entryTime(curTick()), readyTime(curTick()),
< pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
---
> : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
> _masterId(pkt->masterId()),
> read(is_read), rank(_rank), bank(_bank), row(_row),
700c741
< bankRef(bank_ref), rankRef(rank_ref)
---
> bankRef(bank_ref), rankRef(rank_ref), _qosValue(_pkt->qosValue())
704a746,749
> // The DRAM packets are store in a multiple dequeue structure,
> // based on their QoS priority
> typedef std::deque<DRAMPacket*> DRAMPacketQueue;
>
809,810c854
< * @return true if a packet is scheduled to a rank which is available else
< * false
---
> * @return an iterator to the selected packet, else queue.end()
812c856,857
< bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
---
> DRAMPacketQueue::iterator chooseNext(DRAMPacketQueue& queue,
> Tick extra_col_delay);
820,821c865
< * @return true if a packet is scheduled to a rank which is available else
< * false
---
> * @return an iterator to the selected packet, else queue.end()
823c867,868
< bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
---
> DRAMPacketQueue::iterator chooseNextFRFCFS(DRAMPacketQueue& queue,
> Tick extra_col_delay);
835,837c880,881
< std::pair<std::vector<uint32_t>, bool> minBankPrep(
< const std::deque<DRAMPacket*>& queue,
< Tick min_col_at) const;
---
> std::pair<std::vector<uint32_t>, bool>
> minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const;
881c925
< * The controller's main read and write queues
---
> * The controller's main read and write queues, with support for QoS reordering
883,884c927,928
< std::deque<DRAMPacket*> readQueue;
< std::deque<DRAMPacket*> writeQueue;
---
> std::vector<DRAMPacketQueue> readQueue;
> std::vector<DRAMPacketQueue> writeQueue;
898c942
< * responses are stored seperately mostly to keep the code clean
---
> * responses are stored separately mostly to keep the code clean
976c1020
< * Max column accesses (read and write) per row, before forefully
---
> * Max column accesses (read and write) per row, before forcefully
1035a1080,1099
> // per-master bytes read and written to memory
> Stats::Vector masterReadBytes;
> Stats::Vector masterWriteBytes;
>
> // per-master bytes read and written to memory rate
> Stats::Formula masterReadRate;
> Stats::Formula masterWriteRate;
>
> // per-master read and write serviced memory accesses
> Stats::Vector masterReadAccesses;
> Stats::Vector masterWriteAccesses;
>
> // per-master read and write total memory access latency
> Stats::Vector masterReadTotalLat;
> Stats::Vector masterWriteTotalLat;
>
> // per-master raed and write average memory access latency
> Stats::Formula masterReadAvgLat;
> Stats::Formula masterWriteAvgLat;
>
1092c1156
< * @param rank Currrent rank
---
> * @param rank Current rank