44a45
> * Wendy Elsasser
89a91,94
> *
> * The low-power functionality implements a staggered powerdown
> * similar to that described in "Optimized Active and Power-Down Mode
> * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
143d147
< READ_TO_WRITE,
145d148
< WRITE_TO_READ
149a153,155
> /* bus state for next request event triggered */
> BusState busStateNext;
>
200a207,282
> * The power state captures the different operational states of
> * the DRAM and interacts with the bus read/write state machine,
> * and the refresh state machine.
> *
> * PWR_IDLE : The idle state in which all banks are closed
> * From here can transition to: PWR_REF, PWR_ACT,
> * PWR_PRE_PDN
> *
> * PWR_REF : Auto-refresh state. Will transition when refresh is
> * complete based on power state prior to PWR_REF
> * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
> * PWR_SREF
> *
> * PWR_SREF : Self-refresh state. Entered after refresh if
> * previous state was PWR_PRE_PDN
> * From here can transition to: PWR_IDLE
> *
> * PWR_PRE_PDN : Precharge power down state
> * From here can transition to: PWR_REF, PWR_IDLE
> *
> * PWR_ACT : Activate state in which one or more banks are open
> * From here can transition to: PWR_IDLE, PWR_ACT_PDN
> *
> * PWR_ACT_PDN : Activate power down state
> * From here can transition to: PWR_ACT
> */
> enum PowerState {
> PWR_IDLE = 0,
> PWR_REF,
> PWR_SREF,
> PWR_PRE_PDN,
> PWR_ACT,
> PWR_ACT_PDN
> };
>
> /**
> * The refresh state is used to control the progress of the
> * refresh scheduling. When normal operation is in progress the
> * refresh state is idle. Once tREFI has elasped, a refresh event
> * is triggered to start the following STM transitions which are
> * used to issue a refresh and return back to normal operation
> *
> * REF_IDLE : IDLE state used during normal operation
> * From here can transition to: REF_DRAIN
> *
> * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
> * after self-refresh exit completes
> * From here can transition to: REF_DRAIN
> *
> * REF_DRAIN : Drain state in which on going accesses complete.
> * From here can transition to: REF_PD_EXIT
> *
> * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
> * Next state dependent on whether banks are open
> * From here can transition to: REF_PRE, REF_START
> *
> * REF_PRE : Close (precharge) all open banks
> * From here can transition to: REF_START
> *
> * REF_START : Issue refresh command and update DRAMPower stats
> * From here can transition to: REF_RUN
> *
> * REF_RUN : Refresh running, waiting for tRFC to expire
> * From here can transition to: REF_IDLE, REF_SREF_EXIT
> */
> enum RefreshState {
> REF_IDLE = 0,
> REF_DRAIN,
> REF_PD_EXIT,
> REF_SREF_EXIT,
> REF_PRE,
> REF_START,
> REF_RUN
> };
>
> /**
213,247d294
< * The power state captures the different operational states of
< * the DRAM and interacts with the bus read/write state machine,
< * and the refresh state machine. In the idle state all banks are
< * precharged. From there we either go to an auto refresh (as
< * determined by the refresh state machine), or to a precharge
< * power down mode. From idle the memory can also go to the active
< * state (with one or more banks active), and in turn from there
< * to active power down. At the moment we do not capture the deep
< * power down and self-refresh state.
< */
< enum PowerState {
< PWR_IDLE = 0,
< PWR_REF,
< PWR_PRE_PDN,
< PWR_ACT,
< PWR_ACT_PDN
< };
<
< /**
< * The refresh state is used to control the progress of the
< * refresh scheduling. When normal operation is in progress the
< * refresh state is idle. From there, it progresses to the refresh
< * drain state once tREFI has passed. The refresh drain state
< * captures the DRAM row active state, as it will stay there until
< * all ongoing accesses complete. Thereafter all banks are
< * precharged, and lastly, the DRAM is refreshed.
< */
< enum RefreshState {
< REF_IDLE = 0,
< REF_DRAIN,
< REF_PRE,
< REF_RUN
< };
<
< /**
254,258c301
< * track of what power transition is happening at what time, such
< * that we can go back in time and change history. For example, if
< * we precharge all banks and schedule going to the idle state, we
< * might at a later point decide to activate a bank before the
< * transition to idle would have taken place.
---
> * track of what power transition is happening at what time
263c306
< * Current power state.
---
> * Previous low-power state, which will be re-entered after refresh.
265c308
< PowerState pwrState;
---
> PowerState pwrStatePostRefresh;
273,277d315
< * current refresh state
< */
< RefreshState refreshState;
<
< /**
300a339,353
> /*
> * Active Power-Down Energy
> */
> Stats::Scalar actPowerDownEnergy;
>
> /*
> * Precharge Power-Down Energy
> */
> Stats::Scalar prePowerDownEnergy;
>
> /*
> * self Refresh Energy
> */
> Stats::Scalar selfRefreshEnergy;
>
304a358,363
> * Stat to track total DRAM idle time
> *
> */
> Stats::Scalar totalIdleTime;
>
> /**
325a385,399
> * Current power state.
> */
> PowerState pwrState;
>
> /**
> * current refresh state
> */
> RefreshState refreshState;
>
> /**
> * rank is in or transitioning to power-down or self-refresh
> */
> bool inLowPowerState;
>
> /**
329a404,413
> /**
> * Track number of packets in read queue going to this rank
> */
> uint32_t readEntries;
>
> /**
> * Track number of packets in write queue going to this rank
> */
> uint32_t writeEntries;
>
330a415,426
> * Number of ACT, RD, and WR events currently scheduled
> * Incremented when a refresh event is started as well
> * Used to determine when a low-power state can be entered
> */
> uint8_t outstandingEvents;
>
> /**
> * delay power-down and self-refresh exit until this requirement is met
> */
> Tick wakeUpAllowedAt;
>
> /**
379a476,479
> * Rank will be unavailable if refresh is ongoing.
> * This includes refresh events explicitly scheduled from the the
> * controller or memory initiated events which will occur during
> * self-refresh mode.
394a495,517
> * Trigger a self-refresh exit if there are entries enqueued
> * Exit if there are any read entries regardless of the bus state.
> * If we are currently issuing write commands, exit if we have any
> * write commands enqueued as well.
> * Could expand this in the future to analyze state of entire queue
> * if needed.
> *
> * @return boolean indicating self-refresh exit should be scheduled
> */
> bool forceSelfRefreshExit() const {
> return (readEntries != 0) ||
> ((memory.busStateNext == WRITE) && (writeEntries != 0));
> }
>
> /**
> * Check if the current rank is idle and should enter a low-pwer state
> *
> * @param Return true if the there are no read commands in Q
> * and there are no outstanding events
> */
> bool lowPowerEntryReady() const;
>
> /**
417a541,561
> /**
> * Schedule a transition to power-down (sleep)
> *
> * @param pwr_state Power state to transition to
> * @param tick Absolute tick when transition should take place
> */
> void powerDownSleep(PowerState pwr_state, Tick tick);
>
> /**
> * schedule and event to wake-up from power-down or self-refresh
> * and update bank timing parameters
> *
> * @param exit_delay Relative tick defining the delay required between
> * low-power exit and the next command
> */
> void scheduleWakeUpEvent(Tick exit_delay);
>
> void processWriteDoneEvent();
> EventWrapper<Rank, &Rank::processWriteDoneEvent>
> writeDoneEvent;
>
433a578,581
> void processWakeUpEvent();
> EventWrapper<Rank, &Rank::processWakeUpEvent>
> wakeUpEvent;
>
> * Wendy Elsasser
89a91,94
> *
> * The low-power functionality implements a staggered powerdown
> * similar to that described in "Optimized Active and Power-Down Mode
> * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
143d147
< READ_TO_WRITE,
145d148
< WRITE_TO_READ
149a153,155
> /* bus state for next request event triggered */
> BusState busStateNext;
>
200a207,282
> * The power state captures the different operational states of
> * the DRAM and interacts with the bus read/write state machine,
> * and the refresh state machine.
> *
> * PWR_IDLE : The idle state in which all banks are closed
> * From here can transition to: PWR_REF, PWR_ACT,
> * PWR_PRE_PDN
> *
> * PWR_REF : Auto-refresh state. Will transition when refresh is
> * complete based on power state prior to PWR_REF
> * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
> * PWR_SREF
> *
> * PWR_SREF : Self-refresh state. Entered after refresh if
> * previous state was PWR_PRE_PDN
> * From here can transition to: PWR_IDLE
> *
> * PWR_PRE_PDN : Precharge power down state
> * From here can transition to: PWR_REF, PWR_IDLE
> *
> * PWR_ACT : Activate state in which one or more banks are open
> * From here can transition to: PWR_IDLE, PWR_ACT_PDN
> *
> * PWR_ACT_PDN : Activate power down state
> * From here can transition to: PWR_ACT
> */
> enum PowerState {
> PWR_IDLE = 0,
> PWR_REF,
> PWR_SREF,
> PWR_PRE_PDN,
> PWR_ACT,
> PWR_ACT_PDN
> };
>
> /**
> * The refresh state is used to control the progress of the
> * refresh scheduling. When normal operation is in progress the
> * refresh state is idle. Once tREFI has elasped, a refresh event
> * is triggered to start the following STM transitions which are
> * used to issue a refresh and return back to normal operation
> *
> * REF_IDLE : IDLE state used during normal operation
> * From here can transition to: REF_DRAIN
> *
> * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
> * after self-refresh exit completes
> * From here can transition to: REF_DRAIN
> *
> * REF_DRAIN : Drain state in which on going accesses complete.
> * From here can transition to: REF_PD_EXIT
> *
> * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
> * Next state dependent on whether banks are open
> * From here can transition to: REF_PRE, REF_START
> *
> * REF_PRE : Close (precharge) all open banks
> * From here can transition to: REF_START
> *
> * REF_START : Issue refresh command and update DRAMPower stats
> * From here can transition to: REF_RUN
> *
> * REF_RUN : Refresh running, waiting for tRFC to expire
> * From here can transition to: REF_IDLE, REF_SREF_EXIT
> */
> enum RefreshState {
> REF_IDLE = 0,
> REF_DRAIN,
> REF_PD_EXIT,
> REF_SREF_EXIT,
> REF_PRE,
> REF_START,
> REF_RUN
> };
>
> /**
213,247d294
< * The power state captures the different operational states of
< * the DRAM and interacts with the bus read/write state machine,
< * and the refresh state machine. In the idle state all banks are
< * precharged. From there we either go to an auto refresh (as
< * determined by the refresh state machine), or to a precharge
< * power down mode. From idle the memory can also go to the active
< * state (with one or more banks active), and in turn from there
< * to active power down. At the moment we do not capture the deep
< * power down and self-refresh state.
< */
< enum PowerState {
< PWR_IDLE = 0,
< PWR_REF,
< PWR_PRE_PDN,
< PWR_ACT,
< PWR_ACT_PDN
< };
<
< /**
< * The refresh state is used to control the progress of the
< * refresh scheduling. When normal operation is in progress the
< * refresh state is idle. From there, it progresses to the refresh
< * drain state once tREFI has passed. The refresh drain state
< * captures the DRAM row active state, as it will stay there until
< * all ongoing accesses complete. Thereafter all banks are
< * precharged, and lastly, the DRAM is refreshed.
< */
< enum RefreshState {
< REF_IDLE = 0,
< REF_DRAIN,
< REF_PRE,
< REF_RUN
< };
<
< /**
254,258c301
< * track of what power transition is happening at what time, such
< * that we can go back in time and change history. For example, if
< * we precharge all banks and schedule going to the idle state, we
< * might at a later point decide to activate a bank before the
< * transition to idle would have taken place.
---
> * track of what power transition is happening at what time
263c306
< * Current power state.
---
> * Previous low-power state, which will be re-entered after refresh.
265c308
< PowerState pwrState;
---
> PowerState pwrStatePostRefresh;
273,277d315
< * current refresh state
< */
< RefreshState refreshState;
<
< /**
300a339,353
> /*
> * Active Power-Down Energy
> */
> Stats::Scalar actPowerDownEnergy;
>
> /*
> * Precharge Power-Down Energy
> */
> Stats::Scalar prePowerDownEnergy;
>
> /*
> * self Refresh Energy
> */
> Stats::Scalar selfRefreshEnergy;
>
304a358,363
> * Stat to track total DRAM idle time
> *
> */
> Stats::Scalar totalIdleTime;
>
> /**
325a385,399
> * Current power state.
> */
> PowerState pwrState;
>
> /**
> * current refresh state
> */
> RefreshState refreshState;
>
> /**
> * rank is in or transitioning to power-down or self-refresh
> */
> bool inLowPowerState;
>
> /**
329a404,413
> /**
> * Track number of packets in read queue going to this rank
> */
> uint32_t readEntries;
>
> /**
> * Track number of packets in write queue going to this rank
> */
> uint32_t writeEntries;
>
330a415,426
> * Number of ACT, RD, and WR events currently scheduled
> * Incremented when a refresh event is started as well
> * Used to determine when a low-power state can be entered
> */
> uint8_t outstandingEvents;
>
> /**
> * delay power-down and self-refresh exit until this requirement is met
> */
> Tick wakeUpAllowedAt;
>
> /**
379a476,479
> * Rank will be unavailable if refresh is ongoing.
> * This includes refresh events explicitly scheduled from the the
> * controller or memory initiated events which will occur during
> * self-refresh mode.
394a495,517
> * Trigger a self-refresh exit if there are entries enqueued
> * Exit if there are any read entries regardless of the bus state.
> * If we are currently issuing write commands, exit if we have any
> * write commands enqueued as well.
> * Could expand this in the future to analyze state of entire queue
> * if needed.
> *
> * @return boolean indicating self-refresh exit should be scheduled
> */
> bool forceSelfRefreshExit() const {
> return (readEntries != 0) ||
> ((memory.busStateNext == WRITE) && (writeEntries != 0));
> }
>
> /**
> * Check if the current rank is idle and should enter a low-pwer state
> *
> * @param Return true if the there are no read commands in Q
> * and there are no outstanding events
> */
> bool lowPowerEntryReady() const;
>
> /**
417a541,561
> /**
> * Schedule a transition to power-down (sleep)
> *
> * @param pwr_state Power state to transition to
> * @param tick Absolute tick when transition should take place
> */
> void powerDownSleep(PowerState pwr_state, Tick tick);
>
> /**
> * schedule and event to wake-up from power-down or self-refresh
> * and update bank timing parameters
> *
> * @param exit_delay Relative tick defining the delay required between
> * low-power exit and the next command
> */
> void scheduleWakeUpEvent(Tick exit_delay);
>
> void processWriteDoneEvent();
> EventWrapper<Rank, &Rank::processWriteDoneEvent>
> writeDoneEvent;
>
433a578,581
> void processWakeUpEvent();
> EventWrapper<Rank, &Rank::processWakeUpEvent>
> wakeUpEvent;
>