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< * @param switched_cmd_type Command type is changing
---
> * @param extra_col_delay Any extra delay due to a read/write switch
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< bool chooseNext(std::deque<DRAMPacket*>& queue, bool switched_cmd_type);
---
> bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
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< * hits and earliest banks available in DRAM
< * Prioritizes accesses to the same rank as previous burst unless
< * controller is switching command type.
---
> * hits and earliest bursts available in DRAM
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< * @param switched_cmd_type Command type is changing
---
> * @param extra_col_delay Any extra delay due to a read/write switch
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< bool reorderQueue(std::deque<DRAMPacket*>& queue, bool switched_cmd_type);
---
> bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
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< * @param switched_cmd_type Command type is changing
---
> * @param time of seamless burst command
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> * @return boolean indicating burst can issue seamlessly, with no gaps
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< uint64_t minBankPrep(const std::deque<DRAMPacket*>& queue,
< bool switched_cmd_type) const;
---
> std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue,
> Tick min_col_at) const;