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> void processNextReqEvent();
> EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
>
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> void processActivateEvent();
> EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent;
>
> void processPrechargeEvent();
> EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent;
>
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< void processNextReqEvent();
< EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
---
> void processPowerEvent();
> EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent;
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<
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> /**
> * The power state captures the different operational states of
> * the DRAM and interacts with the bus read/write state machine,
> * and the refresh state machine. In the idle state all banks are
> * precharged. From there we either go to an auto refresh (as
> * determined by the refresh state machine), or to a precharge
> * power down mode. From idle the memory can also go to the active
> * state (with one or more banks active), and in turn from there
> * to active power down. At the moment we do not capture the deep
> * power down and self-refresh state.
> */
> enum PowerState {
> PWR_IDLE = 0,
> PWR_REF,
> PWR_PRE_PDN,
> PWR_ACT,
> PWR_ACT_PDN
> };
>
> /**
> * Since we are taking decisions out of order, we need to keep
> * track of what power transition is happening at what time, such
> * that we can go back in time and change history. For example, if
> * we precharge all banks and schedule going to the idle state, we
> * might at a later point decide to activate a bank before the
> * transition to idle would have taken place.
> */
> PowerState pwrStateTrans;
>
> /**
> * Current power state.
> */
> PowerState pwrState;
>
> /**
> * Schedule a power state transition in the future, and
> * potentially override an already scheduled transition.
> *
> * @param pwr_state Power state to transition to
> * @param tick Tick when transition should take place
> */
> void schedulePowerEvent(PowerState pwr_state, Tick tick);
>
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< Stats::Formula prechargeAllPercent;
< Stats::Scalar prechargeAllTime;
---
> Stats::Vector pwrStateTime;
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< // To track number of cycles the DRAM is idle, i.e. all the banks
< // are precharged
< Tick idleStartTick;
---
> // Track when we transitioned to the current power state
> Tick pwrStateTick;