156c156
< static const uint32_t INVALID_ROW = -1;
---
> static const uint32_t NO_ROW = -1;
168c168
< openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0),
---
> openRow(NO_ROW), freeAt(0), tRASDoneAt(0), actAllowedAt(0),
392,399d391
< * Looking at all banks, determine the moment in time when they
< * are all free.
< *
< * @return The tick when all banks are free
< */
< Tick maxBankFreeAt() const;
<
< /**
414c406,407
< void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank);
---
> void recordActivate(Tick act_tick, uint8_t rank, uint8_t bank,
> uint16_t row);
415a409,418
> /**
> * Precharge a given bank and also update when the precharge is
> * done. This will also deal with any stats related to the
> * accesses to the open page.
> *
> * @param bank The bank to precharge
> * @param free_at Time when the precharge is done
> */
> void prechargeBank(Bank& bank, Tick free_at);
>
525a529,551
> /**
> * Keep track of when a refresh is due.
> */
> Tick refreshDueAt;
>
> /**
> * The refresh state is used to control the progress of the
> * refresh scheduling. When normal operation is in progress the
> * refresh state is idle. From there, it progresses to the refresh
> * drain state once tREFI has passed. The refresh drain state
> * captures the DRAM row active state, as it will stay there until
> * all ongoing accesses complete. Thereafter all banks are
> * precharged, and lastly, the DRAM is refreshed.
> */
> enum RefreshState {
> REF_IDLE = 0,
> REF_DRAIN,
> REF_PRE,
> REF_RUN
> };
>
> RefreshState refreshState;
>
600,601c626,629
< // To track number of cycles all the banks are precharged
< Tick startTickPrechargeAll;
---
> // To track number of cycles the DRAM is idle, i.e. all the banks
> // are precharged
> Tick idleStartTick;
>