1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 * Wendy Elsasser
46 * Radhika Jagtap
47 */
48
49/**
50 * @file
51 * DRAMCtrl declaration
52 */
53
54#ifndef __MEM_DRAM_CTRL_HH__
55#define __MEM_DRAM_CTRL_HH__
56
57#include <deque>
58#include <string>
59#include <unordered_set>
| 1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 * Wendy Elsasser
46 * Radhika Jagtap
47 */
48
49/**
50 * @file
51 * DRAMCtrl declaration
52 */
53
54#ifndef __MEM_DRAM_CTRL_HH__
55#define __MEM_DRAM_CTRL_HH__
56
57#include <deque>
58#include <string>
59#include <unordered_set>
|
| 60#include <vector>
|
60
61#include "base/callback.hh"
62#include "base/statistics.hh"
63#include "enums/AddrMap.hh"
64#include "enums/MemSched.hh"
65#include "enums/PageManage.hh"
| 61
62#include "base/callback.hh"
63#include "base/statistics.hh"
64#include "enums/AddrMap.hh"
65#include "enums/MemSched.hh"
66#include "enums/PageManage.hh"
|
66#include "mem/abstract_mem.hh"
| 67#include "mem/drampower.hh"
68#include "mem/qos/mem_ctrl.hh"
|
67#include "mem/qport.hh"
68#include "params/DRAMCtrl.hh"
69#include "sim/eventq.hh"
| 69#include "mem/qport.hh"
70#include "params/DRAMCtrl.hh"
71#include "sim/eventq.hh"
|
70#include "mem/drampower.hh"
| |
71
72/**
73 * The DRAM controller is a single-channel memory controller capturing
74 * the most important timing constraints associated with a
75 * contemporary DRAM. For multi-channel memory systems, the controller
76 * is combined with a crossbar model, with the channel address
77 * interleaving taking part in the crossbar.
78 *
79 * As a basic design principle, this controller
80 * model is not cycle callable, but instead uses events to: 1) decide
81 * when new decisions can be made, 2) when resources become available,
82 * 3) when things are to be considered done, and 4) when to send
83 * things back. Through these simple principles, the model delivers
84 * high performance, and lots of flexibility, allowing users to
85 * evaluate the system impact of a wide range of memory technologies,
86 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
87 *
88 * For more details, please see Hansson et al, "Simulating DRAM
89 * controllers for future system architecture exploration",
90 * Proc. ISPASS, 2014. If you use this model as part of your research
91 * please cite the paper.
92 *
93 * The low-power functionality implements a staggered powerdown
94 * similar to that described in "Optimized Active and Power-Down Mode
95 * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
96 */
| 72
73/**
74 * The DRAM controller is a single-channel memory controller capturing
75 * the most important timing constraints associated with a
76 * contemporary DRAM. For multi-channel memory systems, the controller
77 * is combined with a crossbar model, with the channel address
78 * interleaving taking part in the crossbar.
79 *
80 * As a basic design principle, this controller
81 * model is not cycle callable, but instead uses events to: 1) decide
82 * when new decisions can be made, 2) when resources become available,
83 * 3) when things are to be considered done, and 4) when to send
84 * things back. Through these simple principles, the model delivers
85 * high performance, and lots of flexibility, allowing users to
86 * evaluate the system impact of a wide range of memory technologies,
87 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
88 *
89 * For more details, please see Hansson et al, "Simulating DRAM
90 * controllers for future system architecture exploration",
91 * Proc. ISPASS, 2014. If you use this model as part of your research
92 * please cite the paper.
93 *
94 * The low-power functionality implements a staggered powerdown
95 * similar to that described in "Optimized Active and Power-Down Mode
96 * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
97 */
|
97class DRAMCtrl : public AbstractMemory
| 98class DRAMCtrl : public QoS::MemCtrl
|
98{
99
100 private:
101
102 // For now, make use of a queued slave port to avoid dealing with
103 // flow control for the responses being sent back
104 class MemoryPort : public QueuedSlavePort
105 {
106
107 RespPacketQueue queue;
108 DRAMCtrl& memory;
109
110 public:
111
112 MemoryPort(const std::string& name, DRAMCtrl& _memory);
113
114 protected:
115
116 Tick recvAtomic(PacketPtr pkt);
117
118 void recvFunctional(PacketPtr pkt);
119
120 bool recvTimingReq(PacketPtr);
121
122 virtual AddrRangeList getAddrRanges() const;
123
124 };
125
126 /**
127 * Our incoming port, for a multi-ported controller add a crossbar
128 * in front of it
129 */
130 MemoryPort port;
131
132 /**
| 99{
100
101 private:
102
103 // For now, make use of a queued slave port to avoid dealing with
104 // flow control for the responses being sent back
105 class MemoryPort : public QueuedSlavePort
106 {
107
108 RespPacketQueue queue;
109 DRAMCtrl& memory;
110
111 public:
112
113 MemoryPort(const std::string& name, DRAMCtrl& _memory);
114
115 protected:
116
117 Tick recvAtomic(PacketPtr pkt);
118
119 void recvFunctional(PacketPtr pkt);
120
121 bool recvTimingReq(PacketPtr);
122
123 virtual AddrRangeList getAddrRanges() const;
124
125 };
126
127 /**
128 * Our incoming port, for a multi-ported controller add a crossbar
129 * in front of it
130 */
131 MemoryPort port;
132
133 /**
|
133 * Remeber if the memory system is in timing mode
| 134 * Remember if the memory system is in timing mode
|
134 */
135 bool isTimingMode;
136
137 /**
138 * Remember if we have to retry a request when available.
139 */
140 bool retryRdReq;
141 bool retryWrReq;
142
| 135 */
136 bool isTimingMode;
137
138 /**
139 * Remember if we have to retry a request when available.
140 */
141 bool retryRdReq;
142 bool retryWrReq;
143
|
143 /**
144 * Bus state used to control the read/write switching and drive
145 * the scheduling of the next request.
146 */
147 enum BusState {
148 READ = 0,
149 WRITE,
150 };
| 144 /**/
|
151
| 145
|
152 BusState busState;
153
154 /* bus state for next request event triggered */
155 BusState busStateNext;
156
| |
157 /**
158 * Simple structure to hold the values needed to keep track of
159 * commands for DRAMPower
160 */
161 struct Command {
162 Data::MemCommand::cmds type;
163 uint8_t bank;
164 Tick timeStamp;
165
166 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
167 Tick time_stamp)
168 : type(_type), bank(_bank), timeStamp(time_stamp)
169 { }
170 };
171
172 /**
173 * A basic class to track the bank state, i.e. what row is
174 * currently open (if any), when is the bank free to accept a new
175 * column (read/write) command, when can it be precharged, and
176 * when can it be activated.
177 *
178 * The bank also keeps track of how many bytes have been accessed
179 * in the open row since it was opened.
180 */
181 class Bank
182 {
183
184 public:
185
186 static const uint32_t NO_ROW = -1;
187
188 uint32_t openRow;
189 uint8_t bank;
190 uint8_t bankgr;
191
192 Tick rdAllowedAt;
193 Tick wrAllowedAt;
194 Tick preAllowedAt;
195 Tick actAllowedAt;
196
197 uint32_t rowAccesses;
198 uint32_t bytesAccessed;
199
200 Bank() :
201 openRow(NO_ROW), bank(0), bankgr(0),
202 rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
203 rowAccesses(0), bytesAccessed(0)
204 { }
205 };
206
207
208 /**
209 * The power state captures the different operational states of
210 * the DRAM and interacts with the bus read/write state machine,
211 * and the refresh state machine.
212 *
213 * PWR_IDLE : The idle state in which all banks are closed
214 * From here can transition to: PWR_REF, PWR_ACT,
215 * PWR_PRE_PDN
216 *
217 * PWR_REF : Auto-refresh state. Will transition when refresh is
218 * complete based on power state prior to PWR_REF
219 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
220 * PWR_SREF
221 *
222 * PWR_SREF : Self-refresh state. Entered after refresh if
223 * previous state was PWR_PRE_PDN
224 * From here can transition to: PWR_IDLE
225 *
226 * PWR_PRE_PDN : Precharge power down state
227 * From here can transition to: PWR_REF, PWR_IDLE
228 *
229 * PWR_ACT : Activate state in which one or more banks are open
230 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
231 *
232 * PWR_ACT_PDN : Activate power down state
233 * From here can transition to: PWR_ACT
234 */
235 enum PowerState {
236 PWR_IDLE = 0,
237 PWR_REF,
238 PWR_SREF,
239 PWR_PRE_PDN,
240 PWR_ACT,
241 PWR_ACT_PDN
242 };
243
244 /**
245 * The refresh state is used to control the progress of the
246 * refresh scheduling. When normal operation is in progress the
247 * refresh state is idle. Once tREFI has elasped, a refresh event
248 * is triggered to start the following STM transitions which are
249 * used to issue a refresh and return back to normal operation
250 *
251 * REF_IDLE : IDLE state used during normal operation
252 * From here can transition to: REF_DRAIN
253 *
254 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
255 * after self-refresh exit completes
256 * From here can transition to: REF_DRAIN
257 *
258 * REF_DRAIN : Drain state in which on going accesses complete.
259 * From here can transition to: REF_PD_EXIT
260 *
261 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
262 * Next state dependent on whether banks are open
263 * From here can transition to: REF_PRE, REF_START
264 *
265 * REF_PRE : Close (precharge) all open banks
266 * From here can transition to: REF_START
267 *
268 * REF_START : Issue refresh command and update DRAMPower stats
269 * From here can transition to: REF_RUN
270 *
271 * REF_RUN : Refresh running, waiting for tRFC to expire
272 * From here can transition to: REF_IDLE, REF_SREF_EXIT
273 */
274 enum RefreshState {
275 REF_IDLE = 0,
276 REF_DRAIN,
277 REF_PD_EXIT,
278 REF_SREF_EXIT,
279 REF_PRE,
280 REF_START,
281 REF_RUN
282 };
283
284 /**
285 * Rank class includes a vector of banks. Refresh and Power state
286 * machines are defined per rank. Events required to change the
287 * state of the refresh and power state machine are scheduled per
288 * rank. This class allows the implementation of rank-wise refresh
289 * and rank-wise power-down.
290 */
291 class Rank : public EventManager
292 {
293
294 private:
295
296 /**
297 * A reference to the parent DRAMCtrl instance
298 */
299 DRAMCtrl& memory;
300
301 /**
302 * Since we are taking decisions out of order, we need to keep
303 * track of what power transition is happening at what time
304 */
305 PowerState pwrStateTrans;
306
307 /**
308 * Previous low-power state, which will be re-entered after refresh.
309 */
310 PowerState pwrStatePostRefresh;
311
312 /**
313 * Track when we transitioned to the current power state
314 */
315 Tick pwrStateTick;
316
317 /**
318 * Keep track of when a refresh is due.
319 */
320 Tick refreshDueAt;
321
322 /*
323 * Command energies
324 */
325 Stats::Scalar actEnergy;
326 Stats::Scalar preEnergy;
327 Stats::Scalar readEnergy;
328 Stats::Scalar writeEnergy;
329 Stats::Scalar refreshEnergy;
330
331 /*
332 * Active Background Energy
333 */
334 Stats::Scalar actBackEnergy;
335
336 /*
337 * Precharge Background Energy
338 */
339 Stats::Scalar preBackEnergy;
340
341 /*
342 * Active Power-Down Energy
343 */
344 Stats::Scalar actPowerDownEnergy;
345
346 /*
347 * Precharge Power-Down Energy
348 */
349 Stats::Scalar prePowerDownEnergy;
350
351 /*
352 * self Refresh Energy
353 */
354 Stats::Scalar selfRefreshEnergy;
355
356 Stats::Scalar totalEnergy;
357 Stats::Scalar averagePower;
358
359 /**
360 * Stat to track total DRAM idle time
361 *
362 */
363 Stats::Scalar totalIdleTime;
364
365 /**
366 * Track time spent in each power state.
367 */
368 Stats::Vector pwrStateTime;
369
370 /**
371 * Function to update Power Stats
372 */
373 void updatePowerStats();
374
375 /**
376 * Schedule a power state transition in the future, and
377 * potentially override an already scheduled transition.
378 *
379 * @param pwr_state Power state to transition to
380 * @param tick Tick when transition should take place
381 */
382 void schedulePowerEvent(PowerState pwr_state, Tick tick);
383
384 public:
385
386 /**
387 * Current power state.
388 */
389 PowerState pwrState;
390
391 /**
392 * current refresh state
393 */
394 RefreshState refreshState;
395
396 /**
397 * rank is in or transitioning to power-down or self-refresh
398 */
399 bool inLowPowerState;
400
401 /**
402 * Current Rank index
403 */
404 uint8_t rank;
405
406 /**
407 * Track number of packets in read queue going to this rank
408 */
409 uint32_t readEntries;
410
411 /**
412 * Track number of packets in write queue going to this rank
413 */
414 uint32_t writeEntries;
415
416 /**
417 * Number of ACT, RD, and WR events currently scheduled
418 * Incremented when a refresh event is started as well
419 * Used to determine when a low-power state can be entered
420 */
421 uint8_t outstandingEvents;
422
423 /**
424 * delay power-down and self-refresh exit until this requirement is met
425 */
426 Tick wakeUpAllowedAt;
427
428 /**
429 * One DRAMPower instance per rank
430 */
431 DRAMPower power;
432
433 /**
| 146 /**
147 * Simple structure to hold the values needed to keep track of
148 * commands for DRAMPower
149 */
150 struct Command {
151 Data::MemCommand::cmds type;
152 uint8_t bank;
153 Tick timeStamp;
154
155 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
156 Tick time_stamp)
157 : type(_type), bank(_bank), timeStamp(time_stamp)
158 { }
159 };
160
161 /**
162 * A basic class to track the bank state, i.e. what row is
163 * currently open (if any), when is the bank free to accept a new
164 * column (read/write) command, when can it be precharged, and
165 * when can it be activated.
166 *
167 * The bank also keeps track of how many bytes have been accessed
168 * in the open row since it was opened.
169 */
170 class Bank
171 {
172
173 public:
174
175 static const uint32_t NO_ROW = -1;
176
177 uint32_t openRow;
178 uint8_t bank;
179 uint8_t bankgr;
180
181 Tick rdAllowedAt;
182 Tick wrAllowedAt;
183 Tick preAllowedAt;
184 Tick actAllowedAt;
185
186 uint32_t rowAccesses;
187 uint32_t bytesAccessed;
188
189 Bank() :
190 openRow(NO_ROW), bank(0), bankgr(0),
191 rdAllowedAt(0), wrAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
192 rowAccesses(0), bytesAccessed(0)
193 { }
194 };
195
196
197 /**
198 * The power state captures the different operational states of
199 * the DRAM and interacts with the bus read/write state machine,
200 * and the refresh state machine.
201 *
202 * PWR_IDLE : The idle state in which all banks are closed
203 * From here can transition to: PWR_REF, PWR_ACT,
204 * PWR_PRE_PDN
205 *
206 * PWR_REF : Auto-refresh state. Will transition when refresh is
207 * complete based on power state prior to PWR_REF
208 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
209 * PWR_SREF
210 *
211 * PWR_SREF : Self-refresh state. Entered after refresh if
212 * previous state was PWR_PRE_PDN
213 * From here can transition to: PWR_IDLE
214 *
215 * PWR_PRE_PDN : Precharge power down state
216 * From here can transition to: PWR_REF, PWR_IDLE
217 *
218 * PWR_ACT : Activate state in which one or more banks are open
219 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
220 *
221 * PWR_ACT_PDN : Activate power down state
222 * From here can transition to: PWR_ACT
223 */
224 enum PowerState {
225 PWR_IDLE = 0,
226 PWR_REF,
227 PWR_SREF,
228 PWR_PRE_PDN,
229 PWR_ACT,
230 PWR_ACT_PDN
231 };
232
233 /**
234 * The refresh state is used to control the progress of the
235 * refresh scheduling. When normal operation is in progress the
236 * refresh state is idle. Once tREFI has elasped, a refresh event
237 * is triggered to start the following STM transitions which are
238 * used to issue a refresh and return back to normal operation
239 *
240 * REF_IDLE : IDLE state used during normal operation
241 * From here can transition to: REF_DRAIN
242 *
243 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
244 * after self-refresh exit completes
245 * From here can transition to: REF_DRAIN
246 *
247 * REF_DRAIN : Drain state in which on going accesses complete.
248 * From here can transition to: REF_PD_EXIT
249 *
250 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
251 * Next state dependent on whether banks are open
252 * From here can transition to: REF_PRE, REF_START
253 *
254 * REF_PRE : Close (precharge) all open banks
255 * From here can transition to: REF_START
256 *
257 * REF_START : Issue refresh command and update DRAMPower stats
258 * From here can transition to: REF_RUN
259 *
260 * REF_RUN : Refresh running, waiting for tRFC to expire
261 * From here can transition to: REF_IDLE, REF_SREF_EXIT
262 */
263 enum RefreshState {
264 REF_IDLE = 0,
265 REF_DRAIN,
266 REF_PD_EXIT,
267 REF_SREF_EXIT,
268 REF_PRE,
269 REF_START,
270 REF_RUN
271 };
272
273 /**
274 * Rank class includes a vector of banks. Refresh and Power state
275 * machines are defined per rank. Events required to change the
276 * state of the refresh and power state machine are scheduled per
277 * rank. This class allows the implementation of rank-wise refresh
278 * and rank-wise power-down.
279 */
280 class Rank : public EventManager
281 {
282
283 private:
284
285 /**
286 * A reference to the parent DRAMCtrl instance
287 */
288 DRAMCtrl& memory;
289
290 /**
291 * Since we are taking decisions out of order, we need to keep
292 * track of what power transition is happening at what time
293 */
294 PowerState pwrStateTrans;
295
296 /**
297 * Previous low-power state, which will be re-entered after refresh.
298 */
299 PowerState pwrStatePostRefresh;
300
301 /**
302 * Track when we transitioned to the current power state
303 */
304 Tick pwrStateTick;
305
306 /**
307 * Keep track of when a refresh is due.
308 */
309 Tick refreshDueAt;
310
311 /*
312 * Command energies
313 */
314 Stats::Scalar actEnergy;
315 Stats::Scalar preEnergy;
316 Stats::Scalar readEnergy;
317 Stats::Scalar writeEnergy;
318 Stats::Scalar refreshEnergy;
319
320 /*
321 * Active Background Energy
322 */
323 Stats::Scalar actBackEnergy;
324
325 /*
326 * Precharge Background Energy
327 */
328 Stats::Scalar preBackEnergy;
329
330 /*
331 * Active Power-Down Energy
332 */
333 Stats::Scalar actPowerDownEnergy;
334
335 /*
336 * Precharge Power-Down Energy
337 */
338 Stats::Scalar prePowerDownEnergy;
339
340 /*
341 * self Refresh Energy
342 */
343 Stats::Scalar selfRefreshEnergy;
344
345 Stats::Scalar totalEnergy;
346 Stats::Scalar averagePower;
347
348 /**
349 * Stat to track total DRAM idle time
350 *
351 */
352 Stats::Scalar totalIdleTime;
353
354 /**
355 * Track time spent in each power state.
356 */
357 Stats::Vector pwrStateTime;
358
359 /**
360 * Function to update Power Stats
361 */
362 void updatePowerStats();
363
364 /**
365 * Schedule a power state transition in the future, and
366 * potentially override an already scheduled transition.
367 *
368 * @param pwr_state Power state to transition to
369 * @param tick Tick when transition should take place
370 */
371 void schedulePowerEvent(PowerState pwr_state, Tick tick);
372
373 public:
374
375 /**
376 * Current power state.
377 */
378 PowerState pwrState;
379
380 /**
381 * current refresh state
382 */
383 RefreshState refreshState;
384
385 /**
386 * rank is in or transitioning to power-down or self-refresh
387 */
388 bool inLowPowerState;
389
390 /**
391 * Current Rank index
392 */
393 uint8_t rank;
394
395 /**
396 * Track number of packets in read queue going to this rank
397 */
398 uint32_t readEntries;
399
400 /**
401 * Track number of packets in write queue going to this rank
402 */
403 uint32_t writeEntries;
404
405 /**
406 * Number of ACT, RD, and WR events currently scheduled
407 * Incremented when a refresh event is started as well
408 * Used to determine when a low-power state can be entered
409 */
410 uint8_t outstandingEvents;
411
412 /**
413 * delay power-down and self-refresh exit until this requirement is met
414 */
415 Tick wakeUpAllowedAt;
416
417 /**
418 * One DRAMPower instance per rank
419 */
420 DRAMPower power;
421
422 /**
|
434 * List of comamnds issued, to be sent to DRAMPpower at refresh
| 423 * List of commands issued, to be sent to DRAMPpower at refresh
|
435 * and stats dump. Keep commands here since commands to different
436 * banks are added out of order. Will only pass commands up to
437 * curTick() to DRAMPower after sorting.
438 */
439 std::vector<Command> cmdList;
440
441 /**
442 * Vector of Banks. Each rank is made of several devices which in
443 * term are made from several banks.
444 */
445 std::vector<Bank> banks;
446
447 /**
448 * To track number of banks which are currently active for
449 * this rank.
450 */
451 unsigned int numBanksActive;
452
453 /** List to keep track of activate ticks */
454 std::deque<Tick> actTicks;
455
456 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank);
457
458 const std::string name() const
459 {
460 return csprintf("%s_%d", memory.name(), rank);
461 }
462
463 /**
464 * Kick off accounting for power and refresh states and
465 * schedule initial refresh.
466 *
467 * @param ref_tick Tick for first refresh
468 */
469 void startup(Tick ref_tick);
470
471 /**
472 * Stop the refresh events.
473 */
474 void suspend();
475
476 /**
477 * Check if there is no refresh and no preparation of refresh ongoing
478 * i.e. the refresh state machine is in idle
479 *
480 * @param Return true if the rank is idle from a refresh point of view
481 */
482 bool inRefIdleState() const { return refreshState == REF_IDLE; }
483
484 /**
485 * Check if the current rank has all banks closed and is not
486 * in a low power state
487 *
488 * @param Return true if the rank is idle from a bank
489 * and power point of view
490 */
491 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
492
493 /**
494 * Trigger a self-refresh exit if there are entries enqueued
495 * Exit if there are any read entries regardless of the bus state.
496 * If we are currently issuing write commands, exit if we have any
497 * write commands enqueued as well.
498 * Could expand this in the future to analyze state of entire queue
499 * if needed.
500 *
501 * @return boolean indicating self-refresh exit should be scheduled
502 */
503 bool forceSelfRefreshExit() const {
504 return (readEntries != 0) ||
505 ((memory.busStateNext == WRITE) && (writeEntries != 0));
506 }
507
508 /**
509 * Check if the command queue of current rank is idle
510 *
511 * @param Return true if the there are no commands in Q.
512 * Bus direction determines queue checked.
513 */
514 bool isQueueEmpty() const;
515
516 /**
517 * Let the rank check if it was waiting for requests to drain
518 * to allow it to transition states.
519 */
520 void checkDrainDone();
521
522 /**
523 * Push command out of cmdList queue that are scheduled at
524 * or before curTick() to DRAMPower library
525 * All commands before curTick are guaranteed to be complete
526 * and can safely be flushed.
527 */
528 void flushCmdList();
529
530 /*
531 * Function to register Stats
532 */
533 void regStats();
534
535 /**
536 * Computes stats just prior to dump event
537 */
538 void computeStats();
539
540 /**
541 * Reset stats on a stats event
542 */
543 void resetStats();
544
545 /**
546 * Schedule a transition to power-down (sleep)
547 *
548 * @param pwr_state Power state to transition to
549 * @param tick Absolute tick when transition should take place
550 */
551 void powerDownSleep(PowerState pwr_state, Tick tick);
552
553 /**
554 * schedule and event to wake-up from power-down or self-refresh
555 * and update bank timing parameters
556 *
557 * @param exit_delay Relative tick defining the delay required between
558 * low-power exit and the next command
559 */
560 void scheduleWakeUpEvent(Tick exit_delay);
561
562 void processWriteDoneEvent();
563 EventFunctionWrapper writeDoneEvent;
564
565 void processActivateEvent();
566 EventFunctionWrapper activateEvent;
567
568 void processPrechargeEvent();
569 EventFunctionWrapper prechargeEvent;
570
571 void processRefreshEvent();
572 EventFunctionWrapper refreshEvent;
573
574 void processPowerEvent();
575 EventFunctionWrapper powerEvent;
576
577 void processWakeUpEvent();
578 EventFunctionWrapper wakeUpEvent;
579
580 };
581
582 /**
583 * Define the process to compute stats on a stats dump event, e.g. on
584 * simulation exit or intermediate stats dump. This is defined per rank
585 * as the per rank stats are based on state transition and periodically
586 * updated, requiring re-sync at exit.
587 */
588 class RankDumpCallback : public Callback
589 {
590 Rank *ranks;
591 public:
592 RankDumpCallback(Rank *r) : ranks(r) {}
593 virtual void process() { ranks->computeStats(); };
594 };
595
596 /** Define a process to clear power lib counters on a stats reset */
597 class RankResetCallback : public Callback
598 {
599 private:
600 /** Pointer to the rank, thus we instantiate per rank */
601 Rank *rank;
602
603 public:
604 RankResetCallback(Rank *r) : rank(r) {}
605 virtual void process() { rank->resetStats(); };
606 };
607
608 /** Define a process to store the time on a stats reset */
609 class MemResetCallback : public Callback
610 {
611 private:
612 /** A reference to the DRAMCtrl instance */
613 DRAMCtrl *mem;
614
615 public:
616 MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {}
617 virtual void process() { mem->lastStatsResetTick = curTick(); };
618 };
619
620 /**
621 * A burst helper helps organize and manage a packet that is larger than
622 * the DRAM burst size. A system packet that is larger than the burst size
623 * is split into multiple DRAM packets and all those DRAM packets point to
624 * a single burst helper such that we know when the whole packet is served.
625 */
626 class BurstHelper {
627
628 public:
629
630 /** Number of DRAM bursts requred for a system packet **/
631 const unsigned int burstCount;
632
633 /** Number of DRAM bursts serviced so far for a system packet **/
634 unsigned int burstsServiced;
635
636 BurstHelper(unsigned int _burstCount)
637 : burstCount(_burstCount), burstsServiced(0)
638 { }
639 };
640
641 /**
642 * A DRAM packet stores packets along with the timestamp of when
643 * the packet entered the queue, and also the decoded address.
644 */
645 class DRAMPacket {
646
647 public:
648
649 /** When did request enter the controller */
650 const Tick entryTime;
651
652 /** When will request leave the controller */
653 Tick readyTime;
654
655 /** This comes from the outside world */
656 const PacketPtr pkt;
657
| 424 * and stats dump. Keep commands here since commands to different
425 * banks are added out of order. Will only pass commands up to
426 * curTick() to DRAMPower after sorting.
427 */
428 std::vector<Command> cmdList;
429
430 /**
431 * Vector of Banks. Each rank is made of several devices which in
432 * term are made from several banks.
433 */
434 std::vector<Bank> banks;
435
436 /**
437 * To track number of banks which are currently active for
438 * this rank.
439 */
440 unsigned int numBanksActive;
441
442 /** List to keep track of activate ticks */
443 std::deque<Tick> actTicks;
444
445 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank);
446
447 const std::string name() const
448 {
449 return csprintf("%s_%d", memory.name(), rank);
450 }
451
452 /**
453 * Kick off accounting for power and refresh states and
454 * schedule initial refresh.
455 *
456 * @param ref_tick Tick for first refresh
457 */
458 void startup(Tick ref_tick);
459
460 /**
461 * Stop the refresh events.
462 */
463 void suspend();
464
465 /**
466 * Check if there is no refresh and no preparation of refresh ongoing
467 * i.e. the refresh state machine is in idle
468 *
469 * @param Return true if the rank is idle from a refresh point of view
470 */
471 bool inRefIdleState() const { return refreshState == REF_IDLE; }
472
473 /**
474 * Check if the current rank has all banks closed and is not
475 * in a low power state
476 *
477 * @param Return true if the rank is idle from a bank
478 * and power point of view
479 */
480 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
481
482 /**
483 * Trigger a self-refresh exit if there are entries enqueued
484 * Exit if there are any read entries regardless of the bus state.
485 * If we are currently issuing write commands, exit if we have any
486 * write commands enqueued as well.
487 * Could expand this in the future to analyze state of entire queue
488 * if needed.
489 *
490 * @return boolean indicating self-refresh exit should be scheduled
491 */
492 bool forceSelfRefreshExit() const {
493 return (readEntries != 0) ||
494 ((memory.busStateNext == WRITE) && (writeEntries != 0));
495 }
496
497 /**
498 * Check if the command queue of current rank is idle
499 *
500 * @param Return true if the there are no commands in Q.
501 * Bus direction determines queue checked.
502 */
503 bool isQueueEmpty() const;
504
505 /**
506 * Let the rank check if it was waiting for requests to drain
507 * to allow it to transition states.
508 */
509 void checkDrainDone();
510
511 /**
512 * Push command out of cmdList queue that are scheduled at
513 * or before curTick() to DRAMPower library
514 * All commands before curTick are guaranteed to be complete
515 * and can safely be flushed.
516 */
517 void flushCmdList();
518
519 /*
520 * Function to register Stats
521 */
522 void regStats();
523
524 /**
525 * Computes stats just prior to dump event
526 */
527 void computeStats();
528
529 /**
530 * Reset stats on a stats event
531 */
532 void resetStats();
533
534 /**
535 * Schedule a transition to power-down (sleep)
536 *
537 * @param pwr_state Power state to transition to
538 * @param tick Absolute tick when transition should take place
539 */
540 void powerDownSleep(PowerState pwr_state, Tick tick);
541
542 /**
543 * schedule and event to wake-up from power-down or self-refresh
544 * and update bank timing parameters
545 *
546 * @param exit_delay Relative tick defining the delay required between
547 * low-power exit and the next command
548 */
549 void scheduleWakeUpEvent(Tick exit_delay);
550
551 void processWriteDoneEvent();
552 EventFunctionWrapper writeDoneEvent;
553
554 void processActivateEvent();
555 EventFunctionWrapper activateEvent;
556
557 void processPrechargeEvent();
558 EventFunctionWrapper prechargeEvent;
559
560 void processRefreshEvent();
561 EventFunctionWrapper refreshEvent;
562
563 void processPowerEvent();
564 EventFunctionWrapper powerEvent;
565
566 void processWakeUpEvent();
567 EventFunctionWrapper wakeUpEvent;
568
569 };
570
571 /**
572 * Define the process to compute stats on a stats dump event, e.g. on
573 * simulation exit or intermediate stats dump. This is defined per rank
574 * as the per rank stats are based on state transition and periodically
575 * updated, requiring re-sync at exit.
576 */
577 class RankDumpCallback : public Callback
578 {
579 Rank *ranks;
580 public:
581 RankDumpCallback(Rank *r) : ranks(r) {}
582 virtual void process() { ranks->computeStats(); };
583 };
584
585 /** Define a process to clear power lib counters on a stats reset */
586 class RankResetCallback : public Callback
587 {
588 private:
589 /** Pointer to the rank, thus we instantiate per rank */
590 Rank *rank;
591
592 public:
593 RankResetCallback(Rank *r) : rank(r) {}
594 virtual void process() { rank->resetStats(); };
595 };
596
597 /** Define a process to store the time on a stats reset */
598 class MemResetCallback : public Callback
599 {
600 private:
601 /** A reference to the DRAMCtrl instance */
602 DRAMCtrl *mem;
603
604 public:
605 MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {}
606 virtual void process() { mem->lastStatsResetTick = curTick(); };
607 };
608
609 /**
610 * A burst helper helps organize and manage a packet that is larger than
611 * the DRAM burst size. A system packet that is larger than the burst size
612 * is split into multiple DRAM packets and all those DRAM packets point to
613 * a single burst helper such that we know when the whole packet is served.
614 */
615 class BurstHelper {
616
617 public:
618
619 /** Number of DRAM bursts requred for a system packet **/
620 const unsigned int burstCount;
621
622 /** Number of DRAM bursts serviced so far for a system packet **/
623 unsigned int burstsServiced;
624
625 BurstHelper(unsigned int _burstCount)
626 : burstCount(_burstCount), burstsServiced(0)
627 { }
628 };
629
630 /**
631 * A DRAM packet stores packets along with the timestamp of when
632 * the packet entered the queue, and also the decoded address.
633 */
634 class DRAMPacket {
635
636 public:
637
638 /** When did request enter the controller */
639 const Tick entryTime;
640
641 /** When will request leave the controller */
642 Tick readyTime;
643
644 /** This comes from the outside world */
645 const PacketPtr pkt;
646
|
658 const bool isRead;
| 647 /** MasterID associated with the packet */
648 const MasterID _masterId;
|
659
| 649
|
| 650 const bool read;
651
|
660 /** Will be populated by address decoder */
661 const uint8_t rank;
662 const uint8_t bank;
663 const uint32_t row;
664
665 /**
666 * Bank id is calculated considering banks in all the ranks
667 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
668 * bankId = 8 --> rank1, bank0
669 */
670 const uint16_t bankId;
671
672 /**
673 * The starting address of the DRAM packet.
674 * This address could be unaligned to burst size boundaries. The
675 * reason is to keep the address offset so we can accurately check
676 * incoming read packets with packets in the write queue.
677 */
678 Addr addr;
679
680 /**
681 * The size of this dram packet in bytes
682 * It is always equal or smaller than DRAM burst size
683 */
684 unsigned int size;
685
686 /**
687 * A pointer to the BurstHelper if this DRAMPacket is a split packet
688 * If not a split packet (common case), this is set to NULL
689 */
690 BurstHelper* burstHelper;
691 Bank& bankRef;
692 Rank& rankRef;
693
| 652 /** Will be populated by address decoder */
653 const uint8_t rank;
654 const uint8_t bank;
655 const uint32_t row;
656
657 /**
658 * Bank id is calculated considering banks in all the ranks
659 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
660 * bankId = 8 --> rank1, bank0
661 */
662 const uint16_t bankId;
663
664 /**
665 * The starting address of the DRAM packet.
666 * This address could be unaligned to burst size boundaries. The
667 * reason is to keep the address offset so we can accurately check
668 * incoming read packets with packets in the write queue.
669 */
670 Addr addr;
671
672 /**
673 * The size of this dram packet in bytes
674 * It is always equal or smaller than DRAM burst size
675 */
676 unsigned int size;
677
678 /**
679 * A pointer to the BurstHelper if this DRAMPacket is a split packet
680 * If not a split packet (common case), this is set to NULL
681 */
682 BurstHelper* burstHelper;
683 Bank& bankRef;
684 Rank& rankRef;
685
|
| 686 /**
687 * QoS value of the encapsulated packet read at queuing time
688 */
689 uint8_t _qosValue;
690
691 /**
692 * Set the packet QoS value
693 * (interface compatibility with Packet)
694 */
695 inline void qosValue(const uint8_t qv) { _qosValue = qv; }
696
697 /**
698 * Get the packet QoS value
699 * (interface compatibility with Packet)
700 */
701 inline uint8_t qosValue() const { return _qosValue; }
702
703 /**
704 * Get the packet MasterID
705 * (interface compatibility with Packet)
706 */
707 inline MasterID masterId() const { return _masterId; }
708
709 /**
710 * Get the packet size
711 * (interface compatibility with Packet)
712 */
713 inline unsigned int getSize() const { return size; }
714
715 /**
716 * Get the packet address
717 * (interface compatibility with Packet)
718 */
719 inline Addr getAddr() const { return addr; }
720
721 /**
722 * Return true if its a read packet
723 * (interface compatibility with Packet)
724 */
725 inline bool isRead() const { return read; }
726
727 /**
728 * Return true if its a write packet
729 * (interface compatibility with Packet)
730 */
731 inline bool isWrite() const { return !read; }
732
733
|
694 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
695 uint32_t _row, uint16_t bank_id, Addr _addr,
696 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
| 734 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
735 uint32_t _row, uint16_t bank_id, Addr _addr,
736 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
|
697 : entryTime(curTick()), readyTime(curTick()),
698 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
| 737 : entryTime(curTick()), readyTime(curTick()), pkt(_pkt),
738 _masterId(pkt->masterId()),
739 read(is_read), rank(_rank), bank(_bank), row(_row),
|
699 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
| 740 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
|
700 bankRef(bank_ref), rankRef(rank_ref)
| 741 bankRef(bank_ref), rankRef(rank_ref), _qosValue(_pkt->qosValue())
|
701 { }
702
703 };
704
| 742 { }
743
744 };
745
|
| 746 // The DRAM packets are store in a multiple dequeue structure,
747 // based on their QoS priority
748 typedef std::deque<DRAMPacket*> DRAMPacketQueue;
749
|
705 /**
706 * Bunch of things requires to setup "events" in gem5
707 * When event "respondEvent" occurs for example, the method
708 * processRespondEvent is called; no parameters are allowed
709 * in these methods
710 */
711 void processNextReqEvent();
712 EventFunctionWrapper nextReqEvent;
713
714 void processRespondEvent();
715 EventFunctionWrapper respondEvent;
716
717 /**
718 * Check if the read queue has room for more entries
719 *
720 * @param pktCount The number of entries needed in the read queue
721 * @return true if read queue is full, false otherwise
722 */
723 bool readQueueFull(unsigned int pktCount) const;
724
725 /**
726 * Check if the write queue has room for more entries
727 *
728 * @param pktCount The number of entries needed in the write queue
729 * @return true if write queue is full, false otherwise
730 */
731 bool writeQueueFull(unsigned int pktCount) const;
732
733 /**
734 * When a new read comes in, first check if the write q has a
735 * pending request to the same address.\ If not, decode the
736 * address to populate rank/bank/row, create one or mutliple
737 * "dram_pkt", and push them to the back of the read queue.\
738 * If this is the only
739 * read request in the system, schedule an event to start
740 * servicing it.
741 *
742 * @param pkt The request packet from the outside world
743 * @param pktCount The number of DRAM bursts the pkt
744 * translate to. If pkt size is larger then one full burst,
745 * then pktCount is greater than one.
746 */
747 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
748
749 /**
750 * Decode the incoming pkt, create a dram_pkt and push to the
751 * back of the write queue. \If the write q length is more than
752 * the threshold specified by the user, ie the queue is beginning
753 * to get full, stop reads, and start draining writes.
754 *
755 * @param pkt The request packet from the outside world
756 * @param pktCount The number of DRAM bursts the pkt
757 * translate to. If pkt size is larger then one full burst,
758 * then pktCount is greater than one.
759 */
760 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
761
762 /**
763 * Actually do the DRAM access - figure out the latency it
764 * will take to service the req based on bank state, channel state etc
765 * and then update those states to account for this request.\ Based
766 * on this, update the packet's "readyTime" and move it to the
767 * response q from where it will eventually go back to the outside
768 * world.
769 *
770 * @param pkt The DRAM packet created from the outside world pkt
771 */
772 void doDRAMAccess(DRAMPacket* dram_pkt);
773
774 /**
775 * When a packet reaches its "readyTime" in the response Q,
776 * use the "access()" method in AbstractMemory to actually
777 * create the response packet, and send it back to the outside
778 * world requestor.
779 *
780 * @param pkt The packet from the outside world
781 * @param static_latency Static latency to add before sending the packet
782 */
783 void accessAndRespond(PacketPtr pkt, Tick static_latency);
784
785 /**
786 * Address decoder to figure out physical mapping onto ranks,
787 * banks, and rows. This function is called multiple times on the same
788 * system packet if the pakcet is larger than burst of the memory. The
789 * dramPktAddr is used for the offset within the packet.
790 *
791 * @param pkt The packet from the outside world
792 * @param dramPktAddr The starting address of the DRAM packet
793 * @param size The size of the DRAM packet in bytes
794 * @param isRead Is the request for a read or a write to DRAM
795 * @return A DRAMPacket pointer with the decoded information
796 */
797 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
798 bool isRead);
799
800 /**
801 * The memory schduler/arbiter - picks which request needs to
802 * go next, based on the specified policy such as FCFS or FR-FCFS
803 * and moves it to the head of the queue.
804 * Prioritizes accesses to the same rank as previous burst unless
805 * controller is switching command type.
806 *
807 * @param queue Queued requests to consider
808 * @param extra_col_delay Any extra delay due to a read/write switch
| 750 /**
751 * Bunch of things requires to setup "events" in gem5
752 * When event "respondEvent" occurs for example, the method
753 * processRespondEvent is called; no parameters are allowed
754 * in these methods
755 */
756 void processNextReqEvent();
757 EventFunctionWrapper nextReqEvent;
758
759 void processRespondEvent();
760 EventFunctionWrapper respondEvent;
761
762 /**
763 * Check if the read queue has room for more entries
764 *
765 * @param pktCount The number of entries needed in the read queue
766 * @return true if read queue is full, false otherwise
767 */
768 bool readQueueFull(unsigned int pktCount) const;
769
770 /**
771 * Check if the write queue has room for more entries
772 *
773 * @param pktCount The number of entries needed in the write queue
774 * @return true if write queue is full, false otherwise
775 */
776 bool writeQueueFull(unsigned int pktCount) const;
777
778 /**
779 * When a new read comes in, first check if the write q has a
780 * pending request to the same address.\ If not, decode the
781 * address to populate rank/bank/row, create one or mutliple
782 * "dram_pkt", and push them to the back of the read queue.\
783 * If this is the only
784 * read request in the system, schedule an event to start
785 * servicing it.
786 *
787 * @param pkt The request packet from the outside world
788 * @param pktCount The number of DRAM bursts the pkt
789 * translate to. If pkt size is larger then one full burst,
790 * then pktCount is greater than one.
791 */
792 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
793
794 /**
795 * Decode the incoming pkt, create a dram_pkt and push to the
796 * back of the write queue. \If the write q length is more than
797 * the threshold specified by the user, ie the queue is beginning
798 * to get full, stop reads, and start draining writes.
799 *
800 * @param pkt The request packet from the outside world
801 * @param pktCount The number of DRAM bursts the pkt
802 * translate to. If pkt size is larger then one full burst,
803 * then pktCount is greater than one.
804 */
805 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
806
807 /**
808 * Actually do the DRAM access - figure out the latency it
809 * will take to service the req based on bank state, channel state etc
810 * and then update those states to account for this request.\ Based
811 * on this, update the packet's "readyTime" and move it to the
812 * response q from where it will eventually go back to the outside
813 * world.
814 *
815 * @param pkt The DRAM packet created from the outside world pkt
816 */
817 void doDRAMAccess(DRAMPacket* dram_pkt);
818
819 /**
820 * When a packet reaches its "readyTime" in the response Q,
821 * use the "access()" method in AbstractMemory to actually
822 * create the response packet, and send it back to the outside
823 * world requestor.
824 *
825 * @param pkt The packet from the outside world
826 * @param static_latency Static latency to add before sending the packet
827 */
828 void accessAndRespond(PacketPtr pkt, Tick static_latency);
829
830 /**
831 * Address decoder to figure out physical mapping onto ranks,
832 * banks, and rows. This function is called multiple times on the same
833 * system packet if the pakcet is larger than burst of the memory. The
834 * dramPktAddr is used for the offset within the packet.
835 *
836 * @param pkt The packet from the outside world
837 * @param dramPktAddr The starting address of the DRAM packet
838 * @param size The size of the DRAM packet in bytes
839 * @param isRead Is the request for a read or a write to DRAM
840 * @return A DRAMPacket pointer with the decoded information
841 */
842 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
843 bool isRead);
844
845 /**
846 * The memory schduler/arbiter - picks which request needs to
847 * go next, based on the specified policy such as FCFS or FR-FCFS
848 * and moves it to the head of the queue.
849 * Prioritizes accesses to the same rank as previous burst unless
850 * controller is switching command type.
851 *
852 * @param queue Queued requests to consider
853 * @param extra_col_delay Any extra delay due to a read/write switch
|
809 * @return true if a packet is scheduled to a rank which is available else
810 * false
| 854 * @return an iterator to the selected packet, else queue.end()
|
811 */
| 855 */
|
812 bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
| 856 DRAMPacketQueue::iterator chooseNext(DRAMPacketQueue& queue,
857 Tick extra_col_delay);
|
813
814 /**
815 * For FR-FCFS policy reorder the read/write queue depending on row buffer
816 * hits and earliest bursts available in DRAM
817 *
818 * @param queue Queued requests to consider
819 * @param extra_col_delay Any extra delay due to a read/write switch
| 858
859 /**
860 * For FR-FCFS policy reorder the read/write queue depending on row buffer
861 * hits and earliest bursts available in DRAM
862 *
863 * @param queue Queued requests to consider
864 * @param extra_col_delay Any extra delay due to a read/write switch
|
820 * @return true if a packet is scheduled to a rank which is available else
821 * false
| 865 * @return an iterator to the selected packet, else queue.end()
|
822 */
| 866 */
|
823 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
| 867 DRAMPacketQueue::iterator chooseNextFRFCFS(DRAMPacketQueue& queue,
868 Tick extra_col_delay);
|
824
825 /**
826 * Find which are the earliest banks ready to issue an activate
827 * for the enqueued requests. Assumes maximum of 32 banks per rank
828 * Also checks if the bank is already prepped.
829 *
830 * @param queue Queued requests to consider
831 * @param min_col_at time of seamless burst command
832 * @return One-hot encoded mask of bank indices
833 * @return boolean indicating burst can issue seamlessly, with no gaps
834 */
| 869
870 /**
871 * Find which are the earliest banks ready to issue an activate
872 * for the enqueued requests. Assumes maximum of 32 banks per rank
873 * Also checks if the bank is already prepped.
874 *
875 * @param queue Queued requests to consider
876 * @param min_col_at time of seamless burst command
877 * @return One-hot encoded mask of bank indices
878 * @return boolean indicating burst can issue seamlessly, with no gaps
879 */
|
835 std::pair<std::vector<uint32_t>, bool> minBankPrep(
836 const std::deque<DRAMPacket*>& queue,
837 Tick min_col_at) const;
| 880 std::pair, bool>
881 minBankPrep(const DRAMPacketQueue& queue, Tick min_col_at) const;
|
838
839 /**
840 * Keep track of when row activations happen, in order to enforce
841 * the maximum number of activations in the activation window. The
842 * method updates the time that the banks become available based
843 * on the current limits.
844 *
845 * @param rank_ref Reference to the rank
846 * @param bank_ref Reference to the bank
847 * @param act_tick Time when the activation takes place
848 * @param row Index of the row
849 */
850 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
851 uint32_t row);
852
853 /**
854 * Precharge a given bank and also update when the precharge is
855 * done. This will also deal with any stats related to the
856 * accesses to the open page.
857 *
858 * @param rank_ref The rank to precharge
859 * @param bank_ref The bank to precharge
860 * @param pre_at Time when the precharge takes place
861 * @param trace Is this an auto precharge then do not add to trace
862 */
863 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
864 Tick pre_at, bool trace = true);
865
866 /**
867 * Used for debugging to observe the contents of the queues.
868 */
869 void printQs() const;
870
871 /**
872 * Burst-align an address.
873 *
874 * @param addr The potentially unaligned address
875 *
876 * @return An address aligned to a DRAM burst
877 */
878 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
879
880 /**
| 882
883 /**
884 * Keep track of when row activations happen, in order to enforce
885 * the maximum number of activations in the activation window. The
886 * method updates the time that the banks become available based
887 * on the current limits.
888 *
889 * @param rank_ref Reference to the rank
890 * @param bank_ref Reference to the bank
891 * @param act_tick Time when the activation takes place
892 * @param row Index of the row
893 */
894 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
895 uint32_t row);
896
897 /**
898 * Precharge a given bank and also update when the precharge is
899 * done. This will also deal with any stats related to the
900 * accesses to the open page.
901 *
902 * @param rank_ref The rank to precharge
903 * @param bank_ref The bank to precharge
904 * @param pre_at Time when the precharge takes place
905 * @param trace Is this an auto precharge then do not add to trace
906 */
907 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
908 Tick pre_at, bool trace = true);
909
910 /**
911 * Used for debugging to observe the contents of the queues.
912 */
913 void printQs() const;
914
915 /**
916 * Burst-align an address.
917 *
918 * @param addr The potentially unaligned address
919 *
920 * @return An address aligned to a DRAM burst
921 */
922 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
923
924 /**
|
881 * The controller's main read and write queues
| 925 * The controller's main read and write queues, with support for QoS reordering
|
882 */
| 926 */
|
883 std::deque<DRAMPacket*> readQueue;
884 std::deque<DRAMPacket*> writeQueue;
| 927 std::vector<DRAMPacketQueue> readQueue;
928 std::vector<DRAMPacketQueue> writeQueue;
|
885
886 /**
887 * To avoid iterating over the write queue to check for
888 * overlapping transactions, maintain a set of burst addresses
889 * that are currently queued. Since we merge writes to the same
890 * location we never have more than one address to the same burst
891 * address.
892 */
893 std::unordered_set<Addr> isInWriteQueue;
894
895 /**
896 * Response queue where read packets wait after we're done working
897 * with them, but it's not time to send the response yet. The
| 929
930 /**
931 * To avoid iterating over the write queue to check for
932 * overlapping transactions, maintain a set of burst addresses
933 * that are currently queued. Since we merge writes to the same
934 * location we never have more than one address to the same burst
935 * address.
936 */
937 std::unordered_set<Addr> isInWriteQueue;
938
939 /**
940 * Response queue where read packets wait after we're done working
941 * with them, but it's not time to send the response yet. The
|
898 * responses are stored seperately mostly to keep the code clean
| 942 * responses are stored separately mostly to keep the code clean
|
899 * and help with events scheduling. For all logical purposes such
900 * as sizing the read queue, this and the main read queue need to
901 * be added together.
902 */
903 std::deque<DRAMPacket*> respQueue;
904
905 /**
906 * Vector of ranks
907 */
908 std::vector<Rank*> ranks;
909
910 /**
911 * The following are basic design parameters of the memory
912 * controller, and are initialized based on parameter values.
913 * The rowsPerBank is determined based on the capacity, number of
914 * ranks and banks, the burst size, and the row buffer size.
915 */
916 const uint32_t deviceSize;
917 const uint32_t deviceBusWidth;
918 const uint32_t burstLength;
919 const uint32_t deviceRowBufferSize;
920 const uint32_t devicesPerRank;
921 const uint32_t burstSize;
922 const uint32_t rowBufferSize;
923 const uint32_t columnsPerRowBuffer;
924 const uint32_t columnsPerStripe;
925 const uint32_t ranksPerChannel;
926 const uint32_t bankGroupsPerRank;
927 const bool bankGroupArch;
928 const uint32_t banksPerRank;
929 const uint32_t channels;
930 uint32_t rowsPerBank;
931 const uint32_t readBufferSize;
932 const uint32_t writeBufferSize;
933 const uint32_t writeHighThreshold;
934 const uint32_t writeLowThreshold;
935 const uint32_t minWritesPerSwitch;
936 uint32_t writesThisTime;
937 uint32_t readsThisTime;
938
939 /**
940 * Basic memory timing parameters initialized based on parameter
941 * values.
942 */
943 const Tick M5_CLASS_VAR_USED tCK;
944 const Tick tRTW;
945 const Tick tCS;
946 const Tick tBURST;
947 const Tick tCCD_L_WR;
948 const Tick tCCD_L;
949 const Tick tRCD;
950 const Tick tCL;
951 const Tick tRP;
952 const Tick tRAS;
953 const Tick tWR;
954 const Tick tRTP;
955 const Tick tRFC;
956 const Tick tREFI;
957 const Tick tRRD;
958 const Tick tRRD_L;
959 const Tick tXAW;
960 const Tick tXP;
961 const Tick tXS;
962 const uint32_t activationLimit;
963 const Tick rankToRankDly;
964 const Tick wrToRdDly;
965 const Tick rdToWrDly;
966
967 /**
968 * Memory controller configuration initialized based on parameter
969 * values.
970 */
971 Enums::MemSched memSchedPolicy;
972 Enums::AddrMap addrMapping;
973 Enums::PageManage pageMgmt;
974
975 /**
| 943 * and help with events scheduling. For all logical purposes such
944 * as sizing the read queue, this and the main read queue need to
945 * be added together.
946 */
947 std::deque<DRAMPacket*> respQueue;
948
949 /**
950 * Vector of ranks
951 */
952 std::vector<Rank*> ranks;
953
954 /**
955 * The following are basic design parameters of the memory
956 * controller, and are initialized based on parameter values.
957 * The rowsPerBank is determined based on the capacity, number of
958 * ranks and banks, the burst size, and the row buffer size.
959 */
960 const uint32_t deviceSize;
961 const uint32_t deviceBusWidth;
962 const uint32_t burstLength;
963 const uint32_t deviceRowBufferSize;
964 const uint32_t devicesPerRank;
965 const uint32_t burstSize;
966 const uint32_t rowBufferSize;
967 const uint32_t columnsPerRowBuffer;
968 const uint32_t columnsPerStripe;
969 const uint32_t ranksPerChannel;
970 const uint32_t bankGroupsPerRank;
971 const bool bankGroupArch;
972 const uint32_t banksPerRank;
973 const uint32_t channels;
974 uint32_t rowsPerBank;
975 const uint32_t readBufferSize;
976 const uint32_t writeBufferSize;
977 const uint32_t writeHighThreshold;
978 const uint32_t writeLowThreshold;
979 const uint32_t minWritesPerSwitch;
980 uint32_t writesThisTime;
981 uint32_t readsThisTime;
982
983 /**
984 * Basic memory timing parameters initialized based on parameter
985 * values.
986 */
987 const Tick M5_CLASS_VAR_USED tCK;
988 const Tick tRTW;
989 const Tick tCS;
990 const Tick tBURST;
991 const Tick tCCD_L_WR;
992 const Tick tCCD_L;
993 const Tick tRCD;
994 const Tick tCL;
995 const Tick tRP;
996 const Tick tRAS;
997 const Tick tWR;
998 const Tick tRTP;
999 const Tick tRFC;
1000 const Tick tREFI;
1001 const Tick tRRD;
1002 const Tick tRRD_L;
1003 const Tick tXAW;
1004 const Tick tXP;
1005 const Tick tXS;
1006 const uint32_t activationLimit;
1007 const Tick rankToRankDly;
1008 const Tick wrToRdDly;
1009 const Tick rdToWrDly;
1010
1011 /**
1012 * Memory controller configuration initialized based on parameter
1013 * values.
1014 */
1015 Enums::MemSched memSchedPolicy;
1016 Enums::AddrMap addrMapping;
1017 Enums::PageManage pageMgmt;
1018
1019 /**
|
976 * Max column accesses (read and write) per row, before forefully
| 1020 * Max column accesses (read and write) per row, before forcefully
|
977 * closing it.
978 */
979 const uint32_t maxAccessesPerRow;
980
981 /**
982 * Pipeline latency of the controller frontend. The frontend
983 * contribution is added to writes (that complete when they are in
984 * the write buffer) and reads that are serviced the write buffer.
985 */
986 const Tick frontendLatency;
987
988 /**
989 * Pipeline latency of the backend and PHY. Along with the
990 * frontend contribution, this latency is added to reads serviced
991 * by the DRAM.
992 */
993 const Tick backendLatency;
994
995 /**
996 * Till when must we wait before issuing next RD/WR burst?
997 */
998 Tick nextBurstAt;
999
1000 Tick prevArrival;
1001
1002 /**
1003 * The soonest you have to start thinking about the next request
1004 * is the longest access time that can occur before
1005 * nextBurstAt. Assuming you need to precharge, open a new row,
1006 * and access, it is tRP + tRCD + tCL.
1007 */
1008 Tick nextReqTime;
1009
1010 // All statistics that the model needs to capture
1011 Stats::Scalar readReqs;
1012 Stats::Scalar writeReqs;
1013 Stats::Scalar readBursts;
1014 Stats::Scalar writeBursts;
1015 Stats::Scalar bytesReadDRAM;
1016 Stats::Scalar bytesReadWrQ;
1017 Stats::Scalar bytesWritten;
1018 Stats::Scalar bytesReadSys;
1019 Stats::Scalar bytesWrittenSys;
1020 Stats::Scalar servicedByWrQ;
1021 Stats::Scalar mergedWrBursts;
1022 Stats::Scalar neitherReadNorWrite;
1023 Stats::Vector perBankRdBursts;
1024 Stats::Vector perBankWrBursts;
1025 Stats::Scalar numRdRetry;
1026 Stats::Scalar numWrRetry;
1027 Stats::Scalar totGap;
1028 Stats::Vector readPktSize;
1029 Stats::Vector writePktSize;
1030 Stats::Vector rdQLenPdf;
1031 Stats::Vector wrQLenPdf;
1032 Stats::Histogram bytesPerActivate;
1033 Stats::Histogram rdPerTurnAround;
1034 Stats::Histogram wrPerTurnAround;
1035
| 1021 * closing it.
1022 */
1023 const uint32_t maxAccessesPerRow;
1024
1025 /**
1026 * Pipeline latency of the controller frontend. The frontend
1027 * contribution is added to writes (that complete when they are in
1028 * the write buffer) and reads that are serviced the write buffer.
1029 */
1030 const Tick frontendLatency;
1031
1032 /**
1033 * Pipeline latency of the backend and PHY. Along with the
1034 * frontend contribution, this latency is added to reads serviced
1035 * by the DRAM.
1036 */
1037 const Tick backendLatency;
1038
1039 /**
1040 * Till when must we wait before issuing next RD/WR burst?
1041 */
1042 Tick nextBurstAt;
1043
1044 Tick prevArrival;
1045
1046 /**
1047 * The soonest you have to start thinking about the next request
1048 * is the longest access time that can occur before
1049 * nextBurstAt. Assuming you need to precharge, open a new row,
1050 * and access, it is tRP + tRCD + tCL.
1051 */
1052 Tick nextReqTime;
1053
1054 // All statistics that the model needs to capture
1055 Stats::Scalar readReqs;
1056 Stats::Scalar writeReqs;
1057 Stats::Scalar readBursts;
1058 Stats::Scalar writeBursts;
1059 Stats::Scalar bytesReadDRAM;
1060 Stats::Scalar bytesReadWrQ;
1061 Stats::Scalar bytesWritten;
1062 Stats::Scalar bytesReadSys;
1063 Stats::Scalar bytesWrittenSys;
1064 Stats::Scalar servicedByWrQ;
1065 Stats::Scalar mergedWrBursts;
1066 Stats::Scalar neitherReadNorWrite;
1067 Stats::Vector perBankRdBursts;
1068 Stats::Vector perBankWrBursts;
1069 Stats::Scalar numRdRetry;
1070 Stats::Scalar numWrRetry;
1071 Stats::Scalar totGap;
1072 Stats::Vector readPktSize;
1073 Stats::Vector writePktSize;
1074 Stats::Vector rdQLenPdf;
1075 Stats::Vector wrQLenPdf;
1076 Stats::Histogram bytesPerActivate;
1077 Stats::Histogram rdPerTurnAround;
1078 Stats::Histogram wrPerTurnAround;
1079
|
| 1080 // per-master bytes read and written to memory
1081 Stats::Vector masterReadBytes;
1082 Stats::Vector masterWriteBytes;
1083
1084 // per-master bytes read and written to memory rate
1085 Stats::Formula masterReadRate;
1086 Stats::Formula masterWriteRate;
1087
1088 // per-master read and write serviced memory accesses
1089 Stats::Vector masterReadAccesses;
1090 Stats::Vector masterWriteAccesses;
1091
1092 // per-master read and write total memory access latency
1093 Stats::Vector masterReadTotalLat;
1094 Stats::Vector masterWriteTotalLat;
1095
1096 // per-master raed and write average memory access latency
1097 Stats::Formula masterReadAvgLat;
1098 Stats::Formula masterWriteAvgLat;
1099
|
1036 // Latencies summed over all requests
1037 Stats::Scalar totQLat;
1038 Stats::Scalar totMemAccLat;
1039 Stats::Scalar totBusLat;
1040
1041 // Average latencies per request
1042 Stats::Formula avgQLat;
1043 Stats::Formula avgBusLat;
1044 Stats::Formula avgMemAccLat;
1045
1046 // Average bandwidth
1047 Stats::Formula avgRdBW;
1048 Stats::Formula avgWrBW;
1049 Stats::Formula avgRdBWSys;
1050 Stats::Formula avgWrBWSys;
1051 Stats::Formula peakBW;
1052 Stats::Formula busUtil;
1053 Stats::Formula busUtilRead;
1054 Stats::Formula busUtilWrite;
1055
1056 // Average queue lengths
1057 Stats::Average avgRdQLen;
1058 Stats::Average avgWrQLen;
1059
1060 // Row hit count and rate
1061 Stats::Scalar readRowHits;
1062 Stats::Scalar writeRowHits;
1063 Stats::Formula readRowHitRate;
1064 Stats::Formula writeRowHitRate;
1065 Stats::Formula avgGap;
1066
1067 // DRAM Power Calculation
1068 Stats::Formula pageHitRate;
1069
1070 // Holds the value of the rank of burst issued
1071 uint8_t activeRank;
1072
1073 // timestamp offset
1074 uint64_t timeStampOffset;
1075
1076 /** The time when stats were last reset used to calculate average power */
1077 Tick lastStatsResetTick;
1078
1079 /**
1080 * Upstream caches need this packet until true is returned, so
1081 * hold it for deletion until a subsequent call
1082 */
1083 std::unique_ptr<Packet> pendingDelete;
1084
1085 /**
1086 * This function increments the energy when called. If stats are
1087 * dumped periodically, note accumulated energy values will
1088 * appear in the stats (even if the stats are reset). This is a
1089 * result of the energy values coming from DRAMPower, and there
1090 * is currently no support for resetting the state.
1091 *
| 1100 // Latencies summed over all requests
1101 Stats::Scalar totQLat;
1102 Stats::Scalar totMemAccLat;
1103 Stats::Scalar totBusLat;
1104
1105 // Average latencies per request
1106 Stats::Formula avgQLat;
1107 Stats::Formula avgBusLat;
1108 Stats::Formula avgMemAccLat;
1109
1110 // Average bandwidth
1111 Stats::Formula avgRdBW;
1112 Stats::Formula avgWrBW;
1113 Stats::Formula avgRdBWSys;
1114 Stats::Formula avgWrBWSys;
1115 Stats::Formula peakBW;
1116 Stats::Formula busUtil;
1117 Stats::Formula busUtilRead;
1118 Stats::Formula busUtilWrite;
1119
1120 // Average queue lengths
1121 Stats::Average avgRdQLen;
1122 Stats::Average avgWrQLen;
1123
1124 // Row hit count and rate
1125 Stats::Scalar readRowHits;
1126 Stats::Scalar writeRowHits;
1127 Stats::Formula readRowHitRate;
1128 Stats::Formula writeRowHitRate;
1129 Stats::Formula avgGap;
1130
1131 // DRAM Power Calculation
1132 Stats::Formula pageHitRate;
1133
1134 // Holds the value of the rank of burst issued
1135 uint8_t activeRank;
1136
1137 // timestamp offset
1138 uint64_t timeStampOffset;
1139
1140 /** The time when stats were last reset used to calculate average power */
1141 Tick lastStatsResetTick;
1142
1143 /**
1144 * Upstream caches need this packet until true is returned, so
1145 * hold it for deletion until a subsequent call
1146 */
1147 std::unique_ptr<Packet> pendingDelete;
1148
1149 /**
1150 * This function increments the energy when called. If stats are
1151 * dumped periodically, note accumulated energy values will
1152 * appear in the stats (even if the stats are reset). This is a
1153 * result of the energy values coming from DRAMPower, and there
1154 * is currently no support for resetting the state.
1155 *
|
1092 * @param rank Currrent rank
| 1156 * @param rank Current rank
|
1093 */
1094 void updatePowerStats(Rank& rank_ref);
1095
1096 /**
1097 * Function for sorting Command structures based on timeStamp
1098 *
1099 * @param a Memory Command
1100 * @param next Memory Command
1101 * @return true if timeStamp of Command 1 < timeStamp of Command 2
1102 */
1103 static bool sortTime(const Command& cmd, const Command& cmd_next) {
1104 return cmd.timeStamp < cmd_next.timeStamp;
1105 };
1106
1107 public:
1108
1109 void regStats() override;
1110
1111 DRAMCtrl(const DRAMCtrlParams* p);
1112
1113 DrainState drain() override;
1114
1115 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
1116 PortID idx = InvalidPortID) override;
1117
1118 virtual void init() override;
1119 virtual void startup() override;
1120 virtual void drainResume() override;
1121
1122 /**
1123 * Return true once refresh is complete for all ranks and there are no
1124 * additional commands enqueued. (only evaluated when draining)
1125 * This will ensure that all banks are closed, power state is IDLE, and
1126 * power stats have been updated
1127 *
1128 * @return true if all ranks have refreshed, with no commands enqueued
1129 *
1130 */
1131 bool allRanksDrained() const;
1132
1133 protected:
1134
1135 Tick recvAtomic(PacketPtr pkt);
1136 void recvFunctional(PacketPtr pkt);
1137 bool recvTimingReq(PacketPtr pkt);
1138
1139};
1140
1141#endif //__MEM_DRAM_CTRL_HH__
| 1157 */
1158 void updatePowerStats(Rank& rank_ref);
1159
1160 /**
1161 * Function for sorting Command structures based on timeStamp
1162 *
1163 * @param a Memory Command
1164 * @param next Memory Command
1165 * @return true if timeStamp of Command 1 < timeStamp of Command 2
1166 */
1167 static bool sortTime(const Command& cmd, const Command& cmd_next) {
1168 return cmd.timeStamp < cmd_next.timeStamp;
1169 };
1170
1171 public:
1172
1173 void regStats() override;
1174
1175 DRAMCtrl(const DRAMCtrlParams* p);
1176
1177 DrainState drain() override;
1178
1179 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
1180 PortID idx = InvalidPortID) override;
1181
1182 virtual void init() override;
1183 virtual void startup() override;
1184 virtual void drainResume() override;
1185
1186 /**
1187 * Return true once refresh is complete for all ranks and there are no
1188 * additional commands enqueued. (only evaluated when draining)
1189 * This will ensure that all banks are closed, power state is IDLE, and
1190 * power stats have been updated
1191 *
1192 * @return true if all ranks have refreshed, with no commands enqueued
1193 *
1194 */
1195 bool allRanksDrained() const;
1196
1197 protected:
1198
1199 Tick recvAtomic(PacketPtr pkt);
1200 void recvFunctional(PacketPtr pkt);
1201 bool recvTimingReq(PacketPtr pkt);
1202
1203};
1204
1205#endif //__MEM_DRAM_CTRL_HH__
|