1/*
| 1/*
|
2 * Copyright (c) 2012-2016 ARM Limited
| 2 * Copyright (c) 2012-2017 ARM Limited
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 * Wendy Elsasser
46 * Radhika Jagtap
47 */
48
49/**
50 * @file
51 * DRAMCtrl declaration
52 */
53
54#ifndef __MEM_DRAM_CTRL_HH__
55#define __MEM_DRAM_CTRL_HH__
56
57#include <deque>
58#include <string>
59#include <unordered_set>
60
61#include "base/callback.hh"
62#include "base/statistics.hh"
63#include "enums/AddrMap.hh"
64#include "enums/MemSched.hh"
65#include "enums/PageManage.hh"
66#include "mem/abstract_mem.hh"
67#include "mem/qport.hh"
68#include "params/DRAMCtrl.hh"
69#include "sim/eventq.hh"
70#include "mem/drampower.hh"
71
72/**
73 * The DRAM controller is a single-channel memory controller capturing
74 * the most important timing constraints associated with a
75 * contemporary DRAM. For multi-channel memory systems, the controller
76 * is combined with a crossbar model, with the channel address
77 * interleaving taking part in the crossbar.
78 *
79 * As a basic design principle, this controller
80 * model is not cycle callable, but instead uses events to: 1) decide
81 * when new decisions can be made, 2) when resources become available,
82 * 3) when things are to be considered done, and 4) when to send
83 * things back. Through these simple principles, the model delivers
84 * high performance, and lots of flexibility, allowing users to
85 * evaluate the system impact of a wide range of memory technologies,
86 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
87 *
88 * For more details, please see Hansson et al, "Simulating DRAM
89 * controllers for future system architecture exploration",
90 * Proc. ISPASS, 2014. If you use this model as part of your research
91 * please cite the paper.
92 *
93 * The low-power functionality implements a staggered powerdown
94 * similar to that described in "Optimized Active and Power-Down Mode
95 * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
96 */
97class DRAMCtrl : public AbstractMemory
98{
99
100 private:
101
102 // For now, make use of a queued slave port to avoid dealing with
103 // flow control for the responses being sent back
104 class MemoryPort : public QueuedSlavePort
105 {
106
107 RespPacketQueue queue;
108 DRAMCtrl& memory;
109
110 public:
111
112 MemoryPort(const std::string& name, DRAMCtrl& _memory);
113
114 protected:
115
116 Tick recvAtomic(PacketPtr pkt);
117
118 void recvFunctional(PacketPtr pkt);
119
120 bool recvTimingReq(PacketPtr);
121
122 virtual AddrRangeList getAddrRanges() const;
123
124 };
125
126 /**
127 * Our incoming port, for a multi-ported controller add a crossbar
128 * in front of it
129 */
130 MemoryPort port;
131
132 /**
133 * Remeber if the memory system is in timing mode
134 */
135 bool isTimingMode;
136
137 /**
138 * Remember if we have to retry a request when available.
139 */
140 bool retryRdReq;
141 bool retryWrReq;
142
143 /**
144 * Bus state used to control the read/write switching and drive
145 * the scheduling of the next request.
146 */
147 enum BusState {
148 READ = 0,
149 WRITE,
150 };
151
152 BusState busState;
153
154 /* bus state for next request event triggered */
155 BusState busStateNext;
156
157 /**
158 * Simple structure to hold the values needed to keep track of
159 * commands for DRAMPower
160 */
161 struct Command {
162 Data::MemCommand::cmds type;
163 uint8_t bank;
164 Tick timeStamp;
165
166 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
167 Tick time_stamp)
168 : type(_type), bank(_bank), timeStamp(time_stamp)
169 { }
170 };
171
172 /**
173 * A basic class to track the bank state, i.e. what row is
174 * currently open (if any), when is the bank free to accept a new
175 * column (read/write) command, when can it be precharged, and
176 * when can it be activated.
177 *
178 * The bank also keeps track of how many bytes have been accessed
179 * in the open row since it was opened.
180 */
181 class Bank
182 {
183
184 public:
185
186 static const uint32_t NO_ROW = -1;
187
188 uint32_t openRow;
189 uint8_t bank;
190 uint8_t bankgr;
191
192 Tick colAllowedAt;
193 Tick preAllowedAt;
194 Tick actAllowedAt;
195
196 uint32_t rowAccesses;
197 uint32_t bytesAccessed;
198
199 Bank() :
200 openRow(NO_ROW), bank(0), bankgr(0),
201 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
202 rowAccesses(0), bytesAccessed(0)
203 { }
204 };
205
206
207 /**
208 * The power state captures the different operational states of
209 * the DRAM and interacts with the bus read/write state machine,
210 * and the refresh state machine.
211 *
212 * PWR_IDLE : The idle state in which all banks are closed
213 * From here can transition to: PWR_REF, PWR_ACT,
214 * PWR_PRE_PDN
215 *
216 * PWR_REF : Auto-refresh state. Will transition when refresh is
217 * complete based on power state prior to PWR_REF
218 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
219 * PWR_SREF
220 *
221 * PWR_SREF : Self-refresh state. Entered after refresh if
222 * previous state was PWR_PRE_PDN
223 * From here can transition to: PWR_IDLE
224 *
225 * PWR_PRE_PDN : Precharge power down state
226 * From here can transition to: PWR_REF, PWR_IDLE
227 *
228 * PWR_ACT : Activate state in which one or more banks are open
229 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
230 *
231 * PWR_ACT_PDN : Activate power down state
232 * From here can transition to: PWR_ACT
233 */
234 enum PowerState {
235 PWR_IDLE = 0,
236 PWR_REF,
237 PWR_SREF,
238 PWR_PRE_PDN,
239 PWR_ACT,
240 PWR_ACT_PDN
241 };
242
243 /**
244 * The refresh state is used to control the progress of the
245 * refresh scheduling. When normal operation is in progress the
246 * refresh state is idle. Once tREFI has elasped, a refresh event
247 * is triggered to start the following STM transitions which are
248 * used to issue a refresh and return back to normal operation
249 *
250 * REF_IDLE : IDLE state used during normal operation
251 * From here can transition to: REF_DRAIN
252 *
253 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
254 * after self-refresh exit completes
255 * From here can transition to: REF_DRAIN
256 *
257 * REF_DRAIN : Drain state in which on going accesses complete.
258 * From here can transition to: REF_PD_EXIT
259 *
260 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
261 * Next state dependent on whether banks are open
262 * From here can transition to: REF_PRE, REF_START
263 *
264 * REF_PRE : Close (precharge) all open banks
265 * From here can transition to: REF_START
266 *
267 * REF_START : Issue refresh command and update DRAMPower stats
268 * From here can transition to: REF_RUN
269 *
270 * REF_RUN : Refresh running, waiting for tRFC to expire
271 * From here can transition to: REF_IDLE, REF_SREF_EXIT
272 */
273 enum RefreshState {
274 REF_IDLE = 0,
275 REF_DRAIN,
276 REF_PD_EXIT,
277 REF_SREF_EXIT,
278 REF_PRE,
279 REF_START,
280 REF_RUN
281 };
282
283 /**
284 * Rank class includes a vector of banks. Refresh and Power state
285 * machines are defined per rank. Events required to change the
286 * state of the refresh and power state machine are scheduled per
287 * rank. This class allows the implementation of rank-wise refresh
288 * and rank-wise power-down.
289 */
290 class Rank : public EventManager
291 {
292
293 private:
294
295 /**
296 * A reference to the parent DRAMCtrl instance
297 */
298 DRAMCtrl& memory;
299
300 /**
301 * Since we are taking decisions out of order, we need to keep
302 * track of what power transition is happening at what time
303 */
304 PowerState pwrStateTrans;
305
306 /**
307 * Previous low-power state, which will be re-entered after refresh.
308 */
309 PowerState pwrStatePostRefresh;
310
311 /**
312 * Track when we transitioned to the current power state
313 */
314 Tick pwrStateTick;
315
316 /**
317 * Keep track of when a refresh is due.
318 */
319 Tick refreshDueAt;
320
321 /*
322 * Command energies
323 */
324 Stats::Scalar actEnergy;
325 Stats::Scalar preEnergy;
326 Stats::Scalar readEnergy;
327 Stats::Scalar writeEnergy;
328 Stats::Scalar refreshEnergy;
329
330 /*
331 * Active Background Energy
332 */
333 Stats::Scalar actBackEnergy;
334
335 /*
336 * Precharge Background Energy
337 */
338 Stats::Scalar preBackEnergy;
339
340 /*
341 * Active Power-Down Energy
342 */
343 Stats::Scalar actPowerDownEnergy;
344
345 /*
346 * Precharge Power-Down Energy
347 */
348 Stats::Scalar prePowerDownEnergy;
349
350 /*
351 * self Refresh Energy
352 */
353 Stats::Scalar selfRefreshEnergy;
354
355 Stats::Scalar totalEnergy;
356 Stats::Scalar averagePower;
357
358 /**
359 * Stat to track total DRAM idle time
360 *
361 */
362 Stats::Scalar totalIdleTime;
363
364 /**
365 * Track time spent in each power state.
366 */
367 Stats::Vector pwrStateTime;
368
369 /**
370 * Function to update Power Stats
371 */
372 void updatePowerStats();
373
374 /**
375 * Schedule a power state transition in the future, and
376 * potentially override an already scheduled transition.
377 *
378 * @param pwr_state Power state to transition to
379 * @param tick Tick when transition should take place
380 */
381 void schedulePowerEvent(PowerState pwr_state, Tick tick);
382
383 public:
384
385 /**
386 * Current power state.
387 */
388 PowerState pwrState;
389
390 /**
391 * current refresh state
392 */
393 RefreshState refreshState;
394
395 /**
396 * rank is in or transitioning to power-down or self-refresh
397 */
398 bool inLowPowerState;
399
400 /**
401 * Current Rank index
402 */
403 uint8_t rank;
404
405 /**
406 * Track number of packets in read queue going to this rank
407 */
408 uint32_t readEntries;
409
410 /**
411 * Track number of packets in write queue going to this rank
412 */
413 uint32_t writeEntries;
414
415 /**
416 * Number of ACT, RD, and WR events currently scheduled
417 * Incremented when a refresh event is started as well
418 * Used to determine when a low-power state can be entered
419 */
420 uint8_t outstandingEvents;
421
422 /**
423 * delay power-down and self-refresh exit until this requirement is met
424 */
425 Tick wakeUpAllowedAt;
426
427 /**
428 * One DRAMPower instance per rank
429 */
430 DRAMPower power;
431
432 /**
433 * List of comamnds issued, to be sent to DRAMPpower at refresh
434 * and stats dump. Keep commands here since commands to different
435 * banks are added out of order. Will only pass commands up to
436 * curTick() to DRAMPower after sorting.
437 */
438 std::vector<Command> cmdList;
439
440 /**
441 * Vector of Banks. Each rank is made of several devices which in
442 * term are made from several banks.
443 */
444 std::vector<Bank> banks;
445
446 /**
447 * To track number of banks which are currently active for
448 * this rank.
449 */
450 unsigned int numBanksActive;
451
452 /** List to keep track of activate ticks */
453 std::deque<Tick> actTicks;
454
455 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank);
456
457 const std::string name() const
458 {
459 return csprintf("%s_%d", memory.name(), rank);
460 }
461
462 /**
463 * Kick off accounting for power and refresh states and
464 * schedule initial refresh.
465 *
466 * @param ref_tick Tick for first refresh
467 */
468 void startup(Tick ref_tick);
469
470 /**
471 * Stop the refresh events.
472 */
473 void suspend();
474
475 /**
476 * Check if there is no refresh and no preparation of refresh ongoing
477 * i.e. the refresh state machine is in idle
478 *
479 * @param Return true if the rank is idle from a refresh point of view
480 */
481 bool inRefIdleState() const { return refreshState == REF_IDLE; }
482
483 /**
484 * Check if the current rank has all banks closed and is not
485 * in a low power state
486 *
487 * @param Return true if the rank is idle from a bank
488 * and power point of view
489 */
490 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
491
492 /**
493 * Trigger a self-refresh exit if there are entries enqueued
494 * Exit if there are any read entries regardless of the bus state.
495 * If we are currently issuing write commands, exit if we have any
496 * write commands enqueued as well.
497 * Could expand this in the future to analyze state of entire queue
498 * if needed.
499 *
500 * @return boolean indicating self-refresh exit should be scheduled
501 */
502 bool forceSelfRefreshExit() const {
503 return (readEntries != 0) ||
504 ((memory.busStateNext == WRITE) && (writeEntries != 0));
505 }
506
507 /**
| 3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2013 Amin Farmahini-Farahani
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 * Wendy Elsasser
46 * Radhika Jagtap
47 */
48
49/**
50 * @file
51 * DRAMCtrl declaration
52 */
53
54#ifndef __MEM_DRAM_CTRL_HH__
55#define __MEM_DRAM_CTRL_HH__
56
57#include <deque>
58#include <string>
59#include <unordered_set>
60
61#include "base/callback.hh"
62#include "base/statistics.hh"
63#include "enums/AddrMap.hh"
64#include "enums/MemSched.hh"
65#include "enums/PageManage.hh"
66#include "mem/abstract_mem.hh"
67#include "mem/qport.hh"
68#include "params/DRAMCtrl.hh"
69#include "sim/eventq.hh"
70#include "mem/drampower.hh"
71
72/**
73 * The DRAM controller is a single-channel memory controller capturing
74 * the most important timing constraints associated with a
75 * contemporary DRAM. For multi-channel memory systems, the controller
76 * is combined with a crossbar model, with the channel address
77 * interleaving taking part in the crossbar.
78 *
79 * As a basic design principle, this controller
80 * model is not cycle callable, but instead uses events to: 1) decide
81 * when new decisions can be made, 2) when resources become available,
82 * 3) when things are to be considered done, and 4) when to send
83 * things back. Through these simple principles, the model delivers
84 * high performance, and lots of flexibility, allowing users to
85 * evaluate the system impact of a wide range of memory technologies,
86 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
87 *
88 * For more details, please see Hansson et al, "Simulating DRAM
89 * controllers for future system architecture exploration",
90 * Proc. ISPASS, 2014. If you use this model as part of your research
91 * please cite the paper.
92 *
93 * The low-power functionality implements a staggered powerdown
94 * similar to that described in "Optimized Active and Power-Down Mode
95 * Refresh Control in 3D-DRAMs" by Jung et al, VLSI-SoC, 2014.
96 */
97class DRAMCtrl : public AbstractMemory
98{
99
100 private:
101
102 // For now, make use of a queued slave port to avoid dealing with
103 // flow control for the responses being sent back
104 class MemoryPort : public QueuedSlavePort
105 {
106
107 RespPacketQueue queue;
108 DRAMCtrl& memory;
109
110 public:
111
112 MemoryPort(const std::string& name, DRAMCtrl& _memory);
113
114 protected:
115
116 Tick recvAtomic(PacketPtr pkt);
117
118 void recvFunctional(PacketPtr pkt);
119
120 bool recvTimingReq(PacketPtr);
121
122 virtual AddrRangeList getAddrRanges() const;
123
124 };
125
126 /**
127 * Our incoming port, for a multi-ported controller add a crossbar
128 * in front of it
129 */
130 MemoryPort port;
131
132 /**
133 * Remeber if the memory system is in timing mode
134 */
135 bool isTimingMode;
136
137 /**
138 * Remember if we have to retry a request when available.
139 */
140 bool retryRdReq;
141 bool retryWrReq;
142
143 /**
144 * Bus state used to control the read/write switching and drive
145 * the scheduling of the next request.
146 */
147 enum BusState {
148 READ = 0,
149 WRITE,
150 };
151
152 BusState busState;
153
154 /* bus state for next request event triggered */
155 BusState busStateNext;
156
157 /**
158 * Simple structure to hold the values needed to keep track of
159 * commands for DRAMPower
160 */
161 struct Command {
162 Data::MemCommand::cmds type;
163 uint8_t bank;
164 Tick timeStamp;
165
166 constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
167 Tick time_stamp)
168 : type(_type), bank(_bank), timeStamp(time_stamp)
169 { }
170 };
171
172 /**
173 * A basic class to track the bank state, i.e. what row is
174 * currently open (if any), when is the bank free to accept a new
175 * column (read/write) command, when can it be precharged, and
176 * when can it be activated.
177 *
178 * The bank also keeps track of how many bytes have been accessed
179 * in the open row since it was opened.
180 */
181 class Bank
182 {
183
184 public:
185
186 static const uint32_t NO_ROW = -1;
187
188 uint32_t openRow;
189 uint8_t bank;
190 uint8_t bankgr;
191
192 Tick colAllowedAt;
193 Tick preAllowedAt;
194 Tick actAllowedAt;
195
196 uint32_t rowAccesses;
197 uint32_t bytesAccessed;
198
199 Bank() :
200 openRow(NO_ROW), bank(0), bankgr(0),
201 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
202 rowAccesses(0), bytesAccessed(0)
203 { }
204 };
205
206
207 /**
208 * The power state captures the different operational states of
209 * the DRAM and interacts with the bus read/write state machine,
210 * and the refresh state machine.
211 *
212 * PWR_IDLE : The idle state in which all banks are closed
213 * From here can transition to: PWR_REF, PWR_ACT,
214 * PWR_PRE_PDN
215 *
216 * PWR_REF : Auto-refresh state. Will transition when refresh is
217 * complete based on power state prior to PWR_REF
218 * From here can transition to: PWR_IDLE, PWR_PRE_PDN,
219 * PWR_SREF
220 *
221 * PWR_SREF : Self-refresh state. Entered after refresh if
222 * previous state was PWR_PRE_PDN
223 * From here can transition to: PWR_IDLE
224 *
225 * PWR_PRE_PDN : Precharge power down state
226 * From here can transition to: PWR_REF, PWR_IDLE
227 *
228 * PWR_ACT : Activate state in which one or more banks are open
229 * From here can transition to: PWR_IDLE, PWR_ACT_PDN
230 *
231 * PWR_ACT_PDN : Activate power down state
232 * From here can transition to: PWR_ACT
233 */
234 enum PowerState {
235 PWR_IDLE = 0,
236 PWR_REF,
237 PWR_SREF,
238 PWR_PRE_PDN,
239 PWR_ACT,
240 PWR_ACT_PDN
241 };
242
243 /**
244 * The refresh state is used to control the progress of the
245 * refresh scheduling. When normal operation is in progress the
246 * refresh state is idle. Once tREFI has elasped, a refresh event
247 * is triggered to start the following STM transitions which are
248 * used to issue a refresh and return back to normal operation
249 *
250 * REF_IDLE : IDLE state used during normal operation
251 * From here can transition to: REF_DRAIN
252 *
253 * REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
254 * after self-refresh exit completes
255 * From here can transition to: REF_DRAIN
256 *
257 * REF_DRAIN : Drain state in which on going accesses complete.
258 * From here can transition to: REF_PD_EXIT
259 *
260 * REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
261 * Next state dependent on whether banks are open
262 * From here can transition to: REF_PRE, REF_START
263 *
264 * REF_PRE : Close (precharge) all open banks
265 * From here can transition to: REF_START
266 *
267 * REF_START : Issue refresh command and update DRAMPower stats
268 * From here can transition to: REF_RUN
269 *
270 * REF_RUN : Refresh running, waiting for tRFC to expire
271 * From here can transition to: REF_IDLE, REF_SREF_EXIT
272 */
273 enum RefreshState {
274 REF_IDLE = 0,
275 REF_DRAIN,
276 REF_PD_EXIT,
277 REF_SREF_EXIT,
278 REF_PRE,
279 REF_START,
280 REF_RUN
281 };
282
283 /**
284 * Rank class includes a vector of banks. Refresh and Power state
285 * machines are defined per rank. Events required to change the
286 * state of the refresh and power state machine are scheduled per
287 * rank. This class allows the implementation of rank-wise refresh
288 * and rank-wise power-down.
289 */
290 class Rank : public EventManager
291 {
292
293 private:
294
295 /**
296 * A reference to the parent DRAMCtrl instance
297 */
298 DRAMCtrl& memory;
299
300 /**
301 * Since we are taking decisions out of order, we need to keep
302 * track of what power transition is happening at what time
303 */
304 PowerState pwrStateTrans;
305
306 /**
307 * Previous low-power state, which will be re-entered after refresh.
308 */
309 PowerState pwrStatePostRefresh;
310
311 /**
312 * Track when we transitioned to the current power state
313 */
314 Tick pwrStateTick;
315
316 /**
317 * Keep track of when a refresh is due.
318 */
319 Tick refreshDueAt;
320
321 /*
322 * Command energies
323 */
324 Stats::Scalar actEnergy;
325 Stats::Scalar preEnergy;
326 Stats::Scalar readEnergy;
327 Stats::Scalar writeEnergy;
328 Stats::Scalar refreshEnergy;
329
330 /*
331 * Active Background Energy
332 */
333 Stats::Scalar actBackEnergy;
334
335 /*
336 * Precharge Background Energy
337 */
338 Stats::Scalar preBackEnergy;
339
340 /*
341 * Active Power-Down Energy
342 */
343 Stats::Scalar actPowerDownEnergy;
344
345 /*
346 * Precharge Power-Down Energy
347 */
348 Stats::Scalar prePowerDownEnergy;
349
350 /*
351 * self Refresh Energy
352 */
353 Stats::Scalar selfRefreshEnergy;
354
355 Stats::Scalar totalEnergy;
356 Stats::Scalar averagePower;
357
358 /**
359 * Stat to track total DRAM idle time
360 *
361 */
362 Stats::Scalar totalIdleTime;
363
364 /**
365 * Track time spent in each power state.
366 */
367 Stats::Vector pwrStateTime;
368
369 /**
370 * Function to update Power Stats
371 */
372 void updatePowerStats();
373
374 /**
375 * Schedule a power state transition in the future, and
376 * potentially override an already scheduled transition.
377 *
378 * @param pwr_state Power state to transition to
379 * @param tick Tick when transition should take place
380 */
381 void schedulePowerEvent(PowerState pwr_state, Tick tick);
382
383 public:
384
385 /**
386 * Current power state.
387 */
388 PowerState pwrState;
389
390 /**
391 * current refresh state
392 */
393 RefreshState refreshState;
394
395 /**
396 * rank is in or transitioning to power-down or self-refresh
397 */
398 bool inLowPowerState;
399
400 /**
401 * Current Rank index
402 */
403 uint8_t rank;
404
405 /**
406 * Track number of packets in read queue going to this rank
407 */
408 uint32_t readEntries;
409
410 /**
411 * Track number of packets in write queue going to this rank
412 */
413 uint32_t writeEntries;
414
415 /**
416 * Number of ACT, RD, and WR events currently scheduled
417 * Incremented when a refresh event is started as well
418 * Used to determine when a low-power state can be entered
419 */
420 uint8_t outstandingEvents;
421
422 /**
423 * delay power-down and self-refresh exit until this requirement is met
424 */
425 Tick wakeUpAllowedAt;
426
427 /**
428 * One DRAMPower instance per rank
429 */
430 DRAMPower power;
431
432 /**
433 * List of comamnds issued, to be sent to DRAMPpower at refresh
434 * and stats dump. Keep commands here since commands to different
435 * banks are added out of order. Will only pass commands up to
436 * curTick() to DRAMPower after sorting.
437 */
438 std::vector<Command> cmdList;
439
440 /**
441 * Vector of Banks. Each rank is made of several devices which in
442 * term are made from several banks.
443 */
444 std::vector<Bank> banks;
445
446 /**
447 * To track number of banks which are currently active for
448 * this rank.
449 */
450 unsigned int numBanksActive;
451
452 /** List to keep track of activate ticks */
453 std::deque<Tick> actTicks;
454
455 Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank);
456
457 const std::string name() const
458 {
459 return csprintf("%s_%d", memory.name(), rank);
460 }
461
462 /**
463 * Kick off accounting for power and refresh states and
464 * schedule initial refresh.
465 *
466 * @param ref_tick Tick for first refresh
467 */
468 void startup(Tick ref_tick);
469
470 /**
471 * Stop the refresh events.
472 */
473 void suspend();
474
475 /**
476 * Check if there is no refresh and no preparation of refresh ongoing
477 * i.e. the refresh state machine is in idle
478 *
479 * @param Return true if the rank is idle from a refresh point of view
480 */
481 bool inRefIdleState() const { return refreshState == REF_IDLE; }
482
483 /**
484 * Check if the current rank has all banks closed and is not
485 * in a low power state
486 *
487 * @param Return true if the rank is idle from a bank
488 * and power point of view
489 */
490 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
491
492 /**
493 * Trigger a self-refresh exit if there are entries enqueued
494 * Exit if there are any read entries regardless of the bus state.
495 * If we are currently issuing write commands, exit if we have any
496 * write commands enqueued as well.
497 * Could expand this in the future to analyze state of entire queue
498 * if needed.
499 *
500 * @return boolean indicating self-refresh exit should be scheduled
501 */
502 bool forceSelfRefreshExit() const {
503 return (readEntries != 0) ||
504 ((memory.busStateNext == WRITE) && (writeEntries != 0));
505 }
506
507 /**
|
508 * Check if the current rank is idle and should enter a low-pwer state
| 508 * Check if the command queue of current rank is idle
|
509 *
| 509 *
|
510 * @param Return true if the there are no read commands in Q
511 * and there are no outstanding events
| 510 * @param Return true if the there are no commands in Q.
511 * Bus direction determines queue checked.
|
512 */
| 512 */
|
513 bool lowPowerEntryReady() const;
| 513 bool isQueueEmpty() const;
|
514
515 /**
516 * Let the rank check if it was waiting for requests to drain
517 * to allow it to transition states.
518 */
519 void checkDrainDone();
520
521 /**
522 * Push command out of cmdList queue that are scheduled at
523 * or before curTick() to DRAMPower library
524 * All commands before curTick are guaranteed to be complete
525 * and can safely be flushed.
526 */
527 void flushCmdList();
528
529 /*
530 * Function to register Stats
531 */
532 void regStats();
533
534 /**
535 * Computes stats just prior to dump event
536 */
537 void computeStats();
538
539 /**
540 * Reset stats on a stats event
541 */
542 void resetStats();
543
544 /**
545 * Schedule a transition to power-down (sleep)
546 *
547 * @param pwr_state Power state to transition to
548 * @param tick Absolute tick when transition should take place
549 */
550 void powerDownSleep(PowerState pwr_state, Tick tick);
551
552 /**
553 * schedule and event to wake-up from power-down or self-refresh
554 * and update bank timing parameters
555 *
556 * @param exit_delay Relative tick defining the delay required between
557 * low-power exit and the next command
558 */
559 void scheduleWakeUpEvent(Tick exit_delay);
560
561 void processWriteDoneEvent();
562 EventFunctionWrapper writeDoneEvent;
563
564 void processActivateEvent();
565 EventFunctionWrapper activateEvent;
566
567 void processPrechargeEvent();
568 EventFunctionWrapper prechargeEvent;
569
570 void processRefreshEvent();
571 EventFunctionWrapper refreshEvent;
572
573 void processPowerEvent();
574 EventFunctionWrapper powerEvent;
575
576 void processWakeUpEvent();
577 EventFunctionWrapper wakeUpEvent;
578
579 };
580
581 /**
582 * Define the process to compute stats on a stats dump event, e.g. on
583 * simulation exit or intermediate stats dump. This is defined per rank
584 * as the per rank stats are based on state transition and periodically
585 * updated, requiring re-sync at exit.
586 */
587 class RankDumpCallback : public Callback
588 {
589 Rank *ranks;
590 public:
591 RankDumpCallback(Rank *r) : ranks(r) {}
592 virtual void process() { ranks->computeStats(); };
593 };
594
595 /** Define a process to clear power lib counters on a stats reset */
596 class RankResetCallback : public Callback
597 {
598 private:
599 /** Pointer to the rank, thus we instantiate per rank */
600 Rank *rank;
601
602 public:
603 RankResetCallback(Rank *r) : rank(r) {}
604 virtual void process() { rank->resetStats(); };
605 };
606
607 /** Define a process to store the time on a stats reset */
608 class MemResetCallback : public Callback
609 {
610 private:
611 /** A reference to the DRAMCtrl instance */
612 DRAMCtrl *mem;
613
614 public:
615 MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {}
616 virtual void process() { mem->lastStatsResetTick = curTick(); };
617 };
618
619 /**
620 * A burst helper helps organize and manage a packet that is larger than
621 * the DRAM burst size. A system packet that is larger than the burst size
622 * is split into multiple DRAM packets and all those DRAM packets point to
623 * a single burst helper such that we know when the whole packet is served.
624 */
625 class BurstHelper {
626
627 public:
628
629 /** Number of DRAM bursts requred for a system packet **/
630 const unsigned int burstCount;
631
632 /** Number of DRAM bursts serviced so far for a system packet **/
633 unsigned int burstsServiced;
634
635 BurstHelper(unsigned int _burstCount)
636 : burstCount(_burstCount), burstsServiced(0)
637 { }
638 };
639
640 /**
641 * A DRAM packet stores packets along with the timestamp of when
642 * the packet entered the queue, and also the decoded address.
643 */
644 class DRAMPacket {
645
646 public:
647
648 /** When did request enter the controller */
649 const Tick entryTime;
650
651 /** When will request leave the controller */
652 Tick readyTime;
653
654 /** This comes from the outside world */
655 const PacketPtr pkt;
656
657 const bool isRead;
658
659 /** Will be populated by address decoder */
660 const uint8_t rank;
661 const uint8_t bank;
662 const uint32_t row;
663
664 /**
665 * Bank id is calculated considering banks in all the ranks
666 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
667 * bankId = 8 --> rank1, bank0
668 */
669 const uint16_t bankId;
670
671 /**
672 * The starting address of the DRAM packet.
673 * This address could be unaligned to burst size boundaries. The
674 * reason is to keep the address offset so we can accurately check
675 * incoming read packets with packets in the write queue.
676 */
677 Addr addr;
678
679 /**
680 * The size of this dram packet in bytes
681 * It is always equal or smaller than DRAM burst size
682 */
683 unsigned int size;
684
685 /**
686 * A pointer to the BurstHelper if this DRAMPacket is a split packet
687 * If not a split packet (common case), this is set to NULL
688 */
689 BurstHelper* burstHelper;
690 Bank& bankRef;
691 Rank& rankRef;
692
693 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
694 uint32_t _row, uint16_t bank_id, Addr _addr,
695 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
696 : entryTime(curTick()), readyTime(curTick()),
697 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
698 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
699 bankRef(bank_ref), rankRef(rank_ref)
700 { }
701
702 };
703
704 /**
705 * Bunch of things requires to setup "events" in gem5
706 * When event "respondEvent" occurs for example, the method
707 * processRespondEvent is called; no parameters are allowed
708 * in these methods
709 */
710 void processNextReqEvent();
711 EventFunctionWrapper nextReqEvent;
712
713 void processRespondEvent();
714 EventFunctionWrapper respondEvent;
715
716 /**
717 * Check if the read queue has room for more entries
718 *
719 * @param pktCount The number of entries needed in the read queue
720 * @return true if read queue is full, false otherwise
721 */
722 bool readQueueFull(unsigned int pktCount) const;
723
724 /**
725 * Check if the write queue has room for more entries
726 *
727 * @param pktCount The number of entries needed in the write queue
728 * @return true if write queue is full, false otherwise
729 */
730 bool writeQueueFull(unsigned int pktCount) const;
731
732 /**
733 * When a new read comes in, first check if the write q has a
734 * pending request to the same address.\ If not, decode the
735 * address to populate rank/bank/row, create one or mutliple
736 * "dram_pkt", and push them to the back of the read queue.\
737 * If this is the only
738 * read request in the system, schedule an event to start
739 * servicing it.
740 *
741 * @param pkt The request packet from the outside world
742 * @param pktCount The number of DRAM bursts the pkt
743 * translate to. If pkt size is larger then one full burst,
744 * then pktCount is greater than one.
745 */
746 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
747
748 /**
749 * Decode the incoming pkt, create a dram_pkt and push to the
750 * back of the write queue. \If the write q length is more than
751 * the threshold specified by the user, ie the queue is beginning
752 * to get full, stop reads, and start draining writes.
753 *
754 * @param pkt The request packet from the outside world
755 * @param pktCount The number of DRAM bursts the pkt
756 * translate to. If pkt size is larger then one full burst,
757 * then pktCount is greater than one.
758 */
759 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
760
761 /**
762 * Actually do the DRAM access - figure out the latency it
763 * will take to service the req based on bank state, channel state etc
764 * and then update those states to account for this request.\ Based
765 * on this, update the packet's "readyTime" and move it to the
766 * response q from where it will eventually go back to the outside
767 * world.
768 *
769 * @param pkt The DRAM packet created from the outside world pkt
770 */
771 void doDRAMAccess(DRAMPacket* dram_pkt);
772
773 /**
774 * When a packet reaches its "readyTime" in the response Q,
775 * use the "access()" method in AbstractMemory to actually
776 * create the response packet, and send it back to the outside
777 * world requestor.
778 *
779 * @param pkt The packet from the outside world
780 * @param static_latency Static latency to add before sending the packet
781 */
782 void accessAndRespond(PacketPtr pkt, Tick static_latency);
783
784 /**
785 * Address decoder to figure out physical mapping onto ranks,
786 * banks, and rows. This function is called multiple times on the same
787 * system packet if the pakcet is larger than burst of the memory. The
788 * dramPktAddr is used for the offset within the packet.
789 *
790 * @param pkt The packet from the outside world
791 * @param dramPktAddr The starting address of the DRAM packet
792 * @param size The size of the DRAM packet in bytes
793 * @param isRead Is the request for a read or a write to DRAM
794 * @return A DRAMPacket pointer with the decoded information
795 */
796 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
797 bool isRead);
798
799 /**
800 * The memory schduler/arbiter - picks which request needs to
801 * go next, based on the specified policy such as FCFS or FR-FCFS
802 * and moves it to the head of the queue.
803 * Prioritizes accesses to the same rank as previous burst unless
804 * controller is switching command type.
805 *
806 * @param queue Queued requests to consider
807 * @param extra_col_delay Any extra delay due to a read/write switch
808 * @return true if a packet is scheduled to a rank which is available else
809 * false
810 */
811 bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
812
813 /**
814 * For FR-FCFS policy reorder the read/write queue depending on row buffer
815 * hits and earliest bursts available in DRAM
816 *
817 * @param queue Queued requests to consider
818 * @param extra_col_delay Any extra delay due to a read/write switch
819 * @return true if a packet is scheduled to a rank which is available else
820 * false
821 */
822 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
823
824 /**
825 * Find which are the earliest banks ready to issue an activate
826 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
827 * Also checks if the bank is already prepped.
828 *
829 * @param queue Queued requests to consider
830 * @param time of seamless burst command
831 * @return One-hot encoded mask of bank indices
832 * @return boolean indicating burst can issue seamlessly, with no gaps
833 */
834 std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue,
835 Tick min_col_at) const;
836
837 /**
838 * Keep track of when row activations happen, in order to enforce
839 * the maximum number of activations in the activation window. The
840 * method updates the time that the banks become available based
841 * on the current limits.
842 *
843 * @param rank_ref Reference to the rank
844 * @param bank_ref Reference to the bank
845 * @param act_tick Time when the activation takes place
846 * @param row Index of the row
847 */
848 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
849 uint32_t row);
850
851 /**
852 * Precharge a given bank and also update when the precharge is
853 * done. This will also deal with any stats related to the
854 * accesses to the open page.
855 *
856 * @param rank_ref The rank to precharge
857 * @param bank_ref The bank to precharge
858 * @param pre_at Time when the precharge takes place
859 * @param trace Is this an auto precharge then do not add to trace
860 */
861 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
862 Tick pre_at, bool trace = true);
863
864 /**
865 * Used for debugging to observe the contents of the queues.
866 */
867 void printQs() const;
868
869 /**
870 * Burst-align an address.
871 *
872 * @param addr The potentially unaligned address
873 *
874 * @return An address aligned to a DRAM burst
875 */
876 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
877
878 /**
879 * The controller's main read and write queues
880 */
881 std::deque<DRAMPacket*> readQueue;
882 std::deque<DRAMPacket*> writeQueue;
883
884 /**
885 * To avoid iterating over the write queue to check for
886 * overlapping transactions, maintain a set of burst addresses
887 * that are currently queued. Since we merge writes to the same
888 * location we never have more than one address to the same burst
889 * address.
890 */
891 std::unordered_set<Addr> isInWriteQueue;
892
893 /**
894 * Response queue where read packets wait after we're done working
895 * with them, but it's not time to send the response yet. The
896 * responses are stored seperately mostly to keep the code clean
897 * and help with events scheduling. For all logical purposes such
898 * as sizing the read queue, this and the main read queue need to
899 * be added together.
900 */
901 std::deque<DRAMPacket*> respQueue;
902
903 /**
904 * Vector of ranks
905 */
906 std::vector<Rank*> ranks;
907
908 /**
909 * The following are basic design parameters of the memory
910 * controller, and are initialized based on parameter values.
911 * The rowsPerBank is determined based on the capacity, number of
912 * ranks and banks, the burst size, and the row buffer size.
913 */
914 const uint32_t deviceSize;
915 const uint32_t deviceBusWidth;
916 const uint32_t burstLength;
917 const uint32_t deviceRowBufferSize;
918 const uint32_t devicesPerRank;
919 const uint32_t burstSize;
920 const uint32_t rowBufferSize;
921 const uint32_t columnsPerRowBuffer;
922 const uint32_t columnsPerStripe;
923 const uint32_t ranksPerChannel;
924 const uint32_t bankGroupsPerRank;
925 const bool bankGroupArch;
926 const uint32_t banksPerRank;
927 const uint32_t channels;
928 uint32_t rowsPerBank;
929 const uint32_t readBufferSize;
930 const uint32_t writeBufferSize;
931 const uint32_t writeHighThreshold;
932 const uint32_t writeLowThreshold;
933 const uint32_t minWritesPerSwitch;
934 uint32_t writesThisTime;
935 uint32_t readsThisTime;
936
937 /**
938 * Basic memory timing parameters initialized based on parameter
939 * values.
940 */
941 const Tick M5_CLASS_VAR_USED tCK;
942 const Tick tWTR;
943 const Tick tRTW;
944 const Tick tCS;
945 const Tick tBURST;
946 const Tick tCCD_L;
947 const Tick tRCD;
948 const Tick tCL;
949 const Tick tRP;
950 const Tick tRAS;
951 const Tick tWR;
952 const Tick tRTP;
953 const Tick tRFC;
954 const Tick tREFI;
955 const Tick tRRD;
956 const Tick tRRD_L;
957 const Tick tXAW;
958 const Tick tXP;
959 const Tick tXS;
960 const uint32_t activationLimit;
961
962 /**
963 * Memory controller configuration initialized based on parameter
964 * values.
965 */
966 Enums::MemSched memSchedPolicy;
967 Enums::AddrMap addrMapping;
968 Enums::PageManage pageMgmt;
969
970 /**
971 * Max column accesses (read and write) per row, before forefully
972 * closing it.
973 */
974 const uint32_t maxAccessesPerRow;
975
976 /**
977 * Pipeline latency of the controller frontend. The frontend
978 * contribution is added to writes (that complete when they are in
979 * the write buffer) and reads that are serviced the write buffer.
980 */
981 const Tick frontendLatency;
982
983 /**
984 * Pipeline latency of the backend and PHY. Along with the
985 * frontend contribution, this latency is added to reads serviced
986 * by the DRAM.
987 */
988 const Tick backendLatency;
989
990 /**
991 * Till when has the main data bus been spoken for already?
992 */
993 Tick busBusyUntil;
994
995 Tick prevArrival;
996
997 /**
998 * The soonest you have to start thinking about the next request
999 * is the longest access time that can occur before
1000 * busBusyUntil. Assuming you need to precharge, open a new row,
1001 * and access, it is tRP + tRCD + tCL.
1002 */
1003 Tick nextReqTime;
1004
1005 // All statistics that the model needs to capture
1006 Stats::Scalar readReqs;
1007 Stats::Scalar writeReqs;
1008 Stats::Scalar readBursts;
1009 Stats::Scalar writeBursts;
1010 Stats::Scalar bytesReadDRAM;
1011 Stats::Scalar bytesReadWrQ;
1012 Stats::Scalar bytesWritten;
1013 Stats::Scalar bytesReadSys;
1014 Stats::Scalar bytesWrittenSys;
1015 Stats::Scalar servicedByWrQ;
1016 Stats::Scalar mergedWrBursts;
1017 Stats::Scalar neitherReadNorWrite;
1018 Stats::Vector perBankRdBursts;
1019 Stats::Vector perBankWrBursts;
1020 Stats::Scalar numRdRetry;
1021 Stats::Scalar numWrRetry;
1022 Stats::Scalar totGap;
1023 Stats::Vector readPktSize;
1024 Stats::Vector writePktSize;
1025 Stats::Vector rdQLenPdf;
1026 Stats::Vector wrQLenPdf;
1027 Stats::Histogram bytesPerActivate;
1028 Stats::Histogram rdPerTurnAround;
1029 Stats::Histogram wrPerTurnAround;
1030
1031 // Latencies summed over all requests
1032 Stats::Scalar totQLat;
1033 Stats::Scalar totMemAccLat;
1034 Stats::Scalar totBusLat;
1035
1036 // Average latencies per request
1037 Stats::Formula avgQLat;
1038 Stats::Formula avgBusLat;
1039 Stats::Formula avgMemAccLat;
1040
1041 // Average bandwidth
1042 Stats::Formula avgRdBW;
1043 Stats::Formula avgWrBW;
1044 Stats::Formula avgRdBWSys;
1045 Stats::Formula avgWrBWSys;
1046 Stats::Formula peakBW;
1047 Stats::Formula busUtil;
1048 Stats::Formula busUtilRead;
1049 Stats::Formula busUtilWrite;
1050
1051 // Average queue lengths
1052 Stats::Average avgRdQLen;
1053 Stats::Average avgWrQLen;
1054
1055 // Row hit count and rate
1056 Stats::Scalar readRowHits;
1057 Stats::Scalar writeRowHits;
1058 Stats::Formula readRowHitRate;
1059 Stats::Formula writeRowHitRate;
1060 Stats::Formula avgGap;
1061
1062 // DRAM Power Calculation
1063 Stats::Formula pageHitRate;
1064
1065 // Holds the value of the rank of burst issued
1066 uint8_t activeRank;
1067
1068 // timestamp offset
1069 uint64_t timeStampOffset;
1070
1071 /** The time when stats were last reset used to calculate average power */
1072 Tick lastStatsResetTick;
1073
1074 /**
1075 * Upstream caches need this packet until true is returned, so
1076 * hold it for deletion until a subsequent call
1077 */
1078 std::unique_ptr<Packet> pendingDelete;
1079
1080 /**
1081 * This function increments the energy when called. If stats are
1082 * dumped periodically, note accumulated energy values will
1083 * appear in the stats (even if the stats are reset). This is a
1084 * result of the energy values coming from DRAMPower, and there
1085 * is currently no support for resetting the state.
1086 *
1087 * @param rank Currrent rank
1088 */
1089 void updatePowerStats(Rank& rank_ref);
1090
1091 /**
1092 * Function for sorting Command structures based on timeStamp
1093 *
1094 * @param a Memory Command
1095 * @param next Memory Command
1096 * @return true if timeStamp of Command 1 < timeStamp of Command 2
1097 */
1098 static bool sortTime(const Command& cmd, const Command& cmd_next) {
1099 return cmd.timeStamp < cmd_next.timeStamp;
1100 };
1101
1102 public:
1103
1104 void regStats() override;
1105
1106 DRAMCtrl(const DRAMCtrlParams* p);
1107
1108 DrainState drain() override;
1109
1110 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
1111 PortID idx = InvalidPortID) override;
1112
1113 virtual void init() override;
1114 virtual void startup() override;
1115 virtual void drainResume() override;
1116
1117 /**
1118 * Return true once refresh is complete for all ranks and there are no
1119 * additional commands enqueued. (only evaluated when draining)
1120 * This will ensure that all banks are closed, power state is IDLE, and
1121 * power stats have been updated
1122 *
1123 * @return true if all ranks have refreshed, with no commands enqueued
1124 *
1125 */
1126 bool allRanksDrained() const;
1127
1128 protected:
1129
1130 Tick recvAtomic(PacketPtr pkt);
1131 void recvFunctional(PacketPtr pkt);
1132 bool recvTimingReq(PacketPtr pkt);
1133
1134};
1135
1136#endif //__MEM_DRAM_CTRL_HH__
| 514
515 /**
516 * Let the rank check if it was waiting for requests to drain
517 * to allow it to transition states.
518 */
519 void checkDrainDone();
520
521 /**
522 * Push command out of cmdList queue that are scheduled at
523 * or before curTick() to DRAMPower library
524 * All commands before curTick are guaranteed to be complete
525 * and can safely be flushed.
526 */
527 void flushCmdList();
528
529 /*
530 * Function to register Stats
531 */
532 void regStats();
533
534 /**
535 * Computes stats just prior to dump event
536 */
537 void computeStats();
538
539 /**
540 * Reset stats on a stats event
541 */
542 void resetStats();
543
544 /**
545 * Schedule a transition to power-down (sleep)
546 *
547 * @param pwr_state Power state to transition to
548 * @param tick Absolute tick when transition should take place
549 */
550 void powerDownSleep(PowerState pwr_state, Tick tick);
551
552 /**
553 * schedule and event to wake-up from power-down or self-refresh
554 * and update bank timing parameters
555 *
556 * @param exit_delay Relative tick defining the delay required between
557 * low-power exit and the next command
558 */
559 void scheduleWakeUpEvent(Tick exit_delay);
560
561 void processWriteDoneEvent();
562 EventFunctionWrapper writeDoneEvent;
563
564 void processActivateEvent();
565 EventFunctionWrapper activateEvent;
566
567 void processPrechargeEvent();
568 EventFunctionWrapper prechargeEvent;
569
570 void processRefreshEvent();
571 EventFunctionWrapper refreshEvent;
572
573 void processPowerEvent();
574 EventFunctionWrapper powerEvent;
575
576 void processWakeUpEvent();
577 EventFunctionWrapper wakeUpEvent;
578
579 };
580
581 /**
582 * Define the process to compute stats on a stats dump event, e.g. on
583 * simulation exit or intermediate stats dump. This is defined per rank
584 * as the per rank stats are based on state transition and periodically
585 * updated, requiring re-sync at exit.
586 */
587 class RankDumpCallback : public Callback
588 {
589 Rank *ranks;
590 public:
591 RankDumpCallback(Rank *r) : ranks(r) {}
592 virtual void process() { ranks->computeStats(); };
593 };
594
595 /** Define a process to clear power lib counters on a stats reset */
596 class RankResetCallback : public Callback
597 {
598 private:
599 /** Pointer to the rank, thus we instantiate per rank */
600 Rank *rank;
601
602 public:
603 RankResetCallback(Rank *r) : rank(r) {}
604 virtual void process() { rank->resetStats(); };
605 };
606
607 /** Define a process to store the time on a stats reset */
608 class MemResetCallback : public Callback
609 {
610 private:
611 /** A reference to the DRAMCtrl instance */
612 DRAMCtrl *mem;
613
614 public:
615 MemResetCallback(DRAMCtrl *_mem) : mem(_mem) {}
616 virtual void process() { mem->lastStatsResetTick = curTick(); };
617 };
618
619 /**
620 * A burst helper helps organize and manage a packet that is larger than
621 * the DRAM burst size. A system packet that is larger than the burst size
622 * is split into multiple DRAM packets and all those DRAM packets point to
623 * a single burst helper such that we know when the whole packet is served.
624 */
625 class BurstHelper {
626
627 public:
628
629 /** Number of DRAM bursts requred for a system packet **/
630 const unsigned int burstCount;
631
632 /** Number of DRAM bursts serviced so far for a system packet **/
633 unsigned int burstsServiced;
634
635 BurstHelper(unsigned int _burstCount)
636 : burstCount(_burstCount), burstsServiced(0)
637 { }
638 };
639
640 /**
641 * A DRAM packet stores packets along with the timestamp of when
642 * the packet entered the queue, and also the decoded address.
643 */
644 class DRAMPacket {
645
646 public:
647
648 /** When did request enter the controller */
649 const Tick entryTime;
650
651 /** When will request leave the controller */
652 Tick readyTime;
653
654 /** This comes from the outside world */
655 const PacketPtr pkt;
656
657 const bool isRead;
658
659 /** Will be populated by address decoder */
660 const uint8_t rank;
661 const uint8_t bank;
662 const uint32_t row;
663
664 /**
665 * Bank id is calculated considering banks in all the ranks
666 * eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
667 * bankId = 8 --> rank1, bank0
668 */
669 const uint16_t bankId;
670
671 /**
672 * The starting address of the DRAM packet.
673 * This address could be unaligned to burst size boundaries. The
674 * reason is to keep the address offset so we can accurately check
675 * incoming read packets with packets in the write queue.
676 */
677 Addr addr;
678
679 /**
680 * The size of this dram packet in bytes
681 * It is always equal or smaller than DRAM burst size
682 */
683 unsigned int size;
684
685 /**
686 * A pointer to the BurstHelper if this DRAMPacket is a split packet
687 * If not a split packet (common case), this is set to NULL
688 */
689 BurstHelper* burstHelper;
690 Bank& bankRef;
691 Rank& rankRef;
692
693 DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
694 uint32_t _row, uint16_t bank_id, Addr _addr,
695 unsigned int _size, Bank& bank_ref, Rank& rank_ref)
696 : entryTime(curTick()), readyTime(curTick()),
697 pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
698 bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
699 bankRef(bank_ref), rankRef(rank_ref)
700 { }
701
702 };
703
704 /**
705 * Bunch of things requires to setup "events" in gem5
706 * When event "respondEvent" occurs for example, the method
707 * processRespondEvent is called; no parameters are allowed
708 * in these methods
709 */
710 void processNextReqEvent();
711 EventFunctionWrapper nextReqEvent;
712
713 void processRespondEvent();
714 EventFunctionWrapper respondEvent;
715
716 /**
717 * Check if the read queue has room for more entries
718 *
719 * @param pktCount The number of entries needed in the read queue
720 * @return true if read queue is full, false otherwise
721 */
722 bool readQueueFull(unsigned int pktCount) const;
723
724 /**
725 * Check if the write queue has room for more entries
726 *
727 * @param pktCount The number of entries needed in the write queue
728 * @return true if write queue is full, false otherwise
729 */
730 bool writeQueueFull(unsigned int pktCount) const;
731
732 /**
733 * When a new read comes in, first check if the write q has a
734 * pending request to the same address.\ If not, decode the
735 * address to populate rank/bank/row, create one or mutliple
736 * "dram_pkt", and push them to the back of the read queue.\
737 * If this is the only
738 * read request in the system, schedule an event to start
739 * servicing it.
740 *
741 * @param pkt The request packet from the outside world
742 * @param pktCount The number of DRAM bursts the pkt
743 * translate to. If pkt size is larger then one full burst,
744 * then pktCount is greater than one.
745 */
746 void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
747
748 /**
749 * Decode the incoming pkt, create a dram_pkt and push to the
750 * back of the write queue. \If the write q length is more than
751 * the threshold specified by the user, ie the queue is beginning
752 * to get full, stop reads, and start draining writes.
753 *
754 * @param pkt The request packet from the outside world
755 * @param pktCount The number of DRAM bursts the pkt
756 * translate to. If pkt size is larger then one full burst,
757 * then pktCount is greater than one.
758 */
759 void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
760
761 /**
762 * Actually do the DRAM access - figure out the latency it
763 * will take to service the req based on bank state, channel state etc
764 * and then update those states to account for this request.\ Based
765 * on this, update the packet's "readyTime" and move it to the
766 * response q from where it will eventually go back to the outside
767 * world.
768 *
769 * @param pkt The DRAM packet created from the outside world pkt
770 */
771 void doDRAMAccess(DRAMPacket* dram_pkt);
772
773 /**
774 * When a packet reaches its "readyTime" in the response Q,
775 * use the "access()" method in AbstractMemory to actually
776 * create the response packet, and send it back to the outside
777 * world requestor.
778 *
779 * @param pkt The packet from the outside world
780 * @param static_latency Static latency to add before sending the packet
781 */
782 void accessAndRespond(PacketPtr pkt, Tick static_latency);
783
784 /**
785 * Address decoder to figure out physical mapping onto ranks,
786 * banks, and rows. This function is called multiple times on the same
787 * system packet if the pakcet is larger than burst of the memory. The
788 * dramPktAddr is used for the offset within the packet.
789 *
790 * @param pkt The packet from the outside world
791 * @param dramPktAddr The starting address of the DRAM packet
792 * @param size The size of the DRAM packet in bytes
793 * @param isRead Is the request for a read or a write to DRAM
794 * @return A DRAMPacket pointer with the decoded information
795 */
796 DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
797 bool isRead);
798
799 /**
800 * The memory schduler/arbiter - picks which request needs to
801 * go next, based on the specified policy such as FCFS or FR-FCFS
802 * and moves it to the head of the queue.
803 * Prioritizes accesses to the same rank as previous burst unless
804 * controller is switching command type.
805 *
806 * @param queue Queued requests to consider
807 * @param extra_col_delay Any extra delay due to a read/write switch
808 * @return true if a packet is scheduled to a rank which is available else
809 * false
810 */
811 bool chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
812
813 /**
814 * For FR-FCFS policy reorder the read/write queue depending on row buffer
815 * hits and earliest bursts available in DRAM
816 *
817 * @param queue Queued requests to consider
818 * @param extra_col_delay Any extra delay due to a read/write switch
819 * @return true if a packet is scheduled to a rank which is available else
820 * false
821 */
822 bool reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay);
823
824 /**
825 * Find which are the earliest banks ready to issue an activate
826 * for the enqueued requests. Assumes maximum of 64 banks per DIMM
827 * Also checks if the bank is already prepped.
828 *
829 * @param queue Queued requests to consider
830 * @param time of seamless burst command
831 * @return One-hot encoded mask of bank indices
832 * @return boolean indicating burst can issue seamlessly, with no gaps
833 */
834 std::pair<uint64_t, bool> minBankPrep(const std::deque<DRAMPacket*>& queue,
835 Tick min_col_at) const;
836
837 /**
838 * Keep track of when row activations happen, in order to enforce
839 * the maximum number of activations in the activation window. The
840 * method updates the time that the banks become available based
841 * on the current limits.
842 *
843 * @param rank_ref Reference to the rank
844 * @param bank_ref Reference to the bank
845 * @param act_tick Time when the activation takes place
846 * @param row Index of the row
847 */
848 void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
849 uint32_t row);
850
851 /**
852 * Precharge a given bank and also update when the precharge is
853 * done. This will also deal with any stats related to the
854 * accesses to the open page.
855 *
856 * @param rank_ref The rank to precharge
857 * @param bank_ref The bank to precharge
858 * @param pre_at Time when the precharge takes place
859 * @param trace Is this an auto precharge then do not add to trace
860 */
861 void prechargeBank(Rank& rank_ref, Bank& bank_ref,
862 Tick pre_at, bool trace = true);
863
864 /**
865 * Used for debugging to observe the contents of the queues.
866 */
867 void printQs() const;
868
869 /**
870 * Burst-align an address.
871 *
872 * @param addr The potentially unaligned address
873 *
874 * @return An address aligned to a DRAM burst
875 */
876 Addr burstAlign(Addr addr) const { return (addr & ~(Addr(burstSize - 1))); }
877
878 /**
879 * The controller's main read and write queues
880 */
881 std::deque<DRAMPacket*> readQueue;
882 std::deque<DRAMPacket*> writeQueue;
883
884 /**
885 * To avoid iterating over the write queue to check for
886 * overlapping transactions, maintain a set of burst addresses
887 * that are currently queued. Since we merge writes to the same
888 * location we never have more than one address to the same burst
889 * address.
890 */
891 std::unordered_set<Addr> isInWriteQueue;
892
893 /**
894 * Response queue where read packets wait after we're done working
895 * with them, but it's not time to send the response yet. The
896 * responses are stored seperately mostly to keep the code clean
897 * and help with events scheduling. For all logical purposes such
898 * as sizing the read queue, this and the main read queue need to
899 * be added together.
900 */
901 std::deque<DRAMPacket*> respQueue;
902
903 /**
904 * Vector of ranks
905 */
906 std::vector<Rank*> ranks;
907
908 /**
909 * The following are basic design parameters of the memory
910 * controller, and are initialized based on parameter values.
911 * The rowsPerBank is determined based on the capacity, number of
912 * ranks and banks, the burst size, and the row buffer size.
913 */
914 const uint32_t deviceSize;
915 const uint32_t deviceBusWidth;
916 const uint32_t burstLength;
917 const uint32_t deviceRowBufferSize;
918 const uint32_t devicesPerRank;
919 const uint32_t burstSize;
920 const uint32_t rowBufferSize;
921 const uint32_t columnsPerRowBuffer;
922 const uint32_t columnsPerStripe;
923 const uint32_t ranksPerChannel;
924 const uint32_t bankGroupsPerRank;
925 const bool bankGroupArch;
926 const uint32_t banksPerRank;
927 const uint32_t channels;
928 uint32_t rowsPerBank;
929 const uint32_t readBufferSize;
930 const uint32_t writeBufferSize;
931 const uint32_t writeHighThreshold;
932 const uint32_t writeLowThreshold;
933 const uint32_t minWritesPerSwitch;
934 uint32_t writesThisTime;
935 uint32_t readsThisTime;
936
937 /**
938 * Basic memory timing parameters initialized based on parameter
939 * values.
940 */
941 const Tick M5_CLASS_VAR_USED tCK;
942 const Tick tWTR;
943 const Tick tRTW;
944 const Tick tCS;
945 const Tick tBURST;
946 const Tick tCCD_L;
947 const Tick tRCD;
948 const Tick tCL;
949 const Tick tRP;
950 const Tick tRAS;
951 const Tick tWR;
952 const Tick tRTP;
953 const Tick tRFC;
954 const Tick tREFI;
955 const Tick tRRD;
956 const Tick tRRD_L;
957 const Tick tXAW;
958 const Tick tXP;
959 const Tick tXS;
960 const uint32_t activationLimit;
961
962 /**
963 * Memory controller configuration initialized based on parameter
964 * values.
965 */
966 Enums::MemSched memSchedPolicy;
967 Enums::AddrMap addrMapping;
968 Enums::PageManage pageMgmt;
969
970 /**
971 * Max column accesses (read and write) per row, before forefully
972 * closing it.
973 */
974 const uint32_t maxAccessesPerRow;
975
976 /**
977 * Pipeline latency of the controller frontend. The frontend
978 * contribution is added to writes (that complete when they are in
979 * the write buffer) and reads that are serviced the write buffer.
980 */
981 const Tick frontendLatency;
982
983 /**
984 * Pipeline latency of the backend and PHY. Along with the
985 * frontend contribution, this latency is added to reads serviced
986 * by the DRAM.
987 */
988 const Tick backendLatency;
989
990 /**
991 * Till when has the main data bus been spoken for already?
992 */
993 Tick busBusyUntil;
994
995 Tick prevArrival;
996
997 /**
998 * The soonest you have to start thinking about the next request
999 * is the longest access time that can occur before
1000 * busBusyUntil. Assuming you need to precharge, open a new row,
1001 * and access, it is tRP + tRCD + tCL.
1002 */
1003 Tick nextReqTime;
1004
1005 // All statistics that the model needs to capture
1006 Stats::Scalar readReqs;
1007 Stats::Scalar writeReqs;
1008 Stats::Scalar readBursts;
1009 Stats::Scalar writeBursts;
1010 Stats::Scalar bytesReadDRAM;
1011 Stats::Scalar bytesReadWrQ;
1012 Stats::Scalar bytesWritten;
1013 Stats::Scalar bytesReadSys;
1014 Stats::Scalar bytesWrittenSys;
1015 Stats::Scalar servicedByWrQ;
1016 Stats::Scalar mergedWrBursts;
1017 Stats::Scalar neitherReadNorWrite;
1018 Stats::Vector perBankRdBursts;
1019 Stats::Vector perBankWrBursts;
1020 Stats::Scalar numRdRetry;
1021 Stats::Scalar numWrRetry;
1022 Stats::Scalar totGap;
1023 Stats::Vector readPktSize;
1024 Stats::Vector writePktSize;
1025 Stats::Vector rdQLenPdf;
1026 Stats::Vector wrQLenPdf;
1027 Stats::Histogram bytesPerActivate;
1028 Stats::Histogram rdPerTurnAround;
1029 Stats::Histogram wrPerTurnAround;
1030
1031 // Latencies summed over all requests
1032 Stats::Scalar totQLat;
1033 Stats::Scalar totMemAccLat;
1034 Stats::Scalar totBusLat;
1035
1036 // Average latencies per request
1037 Stats::Formula avgQLat;
1038 Stats::Formula avgBusLat;
1039 Stats::Formula avgMemAccLat;
1040
1041 // Average bandwidth
1042 Stats::Formula avgRdBW;
1043 Stats::Formula avgWrBW;
1044 Stats::Formula avgRdBWSys;
1045 Stats::Formula avgWrBWSys;
1046 Stats::Formula peakBW;
1047 Stats::Formula busUtil;
1048 Stats::Formula busUtilRead;
1049 Stats::Formula busUtilWrite;
1050
1051 // Average queue lengths
1052 Stats::Average avgRdQLen;
1053 Stats::Average avgWrQLen;
1054
1055 // Row hit count and rate
1056 Stats::Scalar readRowHits;
1057 Stats::Scalar writeRowHits;
1058 Stats::Formula readRowHitRate;
1059 Stats::Formula writeRowHitRate;
1060 Stats::Formula avgGap;
1061
1062 // DRAM Power Calculation
1063 Stats::Formula pageHitRate;
1064
1065 // Holds the value of the rank of burst issued
1066 uint8_t activeRank;
1067
1068 // timestamp offset
1069 uint64_t timeStampOffset;
1070
1071 /** The time when stats were last reset used to calculate average power */
1072 Tick lastStatsResetTick;
1073
1074 /**
1075 * Upstream caches need this packet until true is returned, so
1076 * hold it for deletion until a subsequent call
1077 */
1078 std::unique_ptr<Packet> pendingDelete;
1079
1080 /**
1081 * This function increments the energy when called. If stats are
1082 * dumped periodically, note accumulated energy values will
1083 * appear in the stats (even if the stats are reset). This is a
1084 * result of the energy values coming from DRAMPower, and there
1085 * is currently no support for resetting the state.
1086 *
1087 * @param rank Currrent rank
1088 */
1089 void updatePowerStats(Rank& rank_ref);
1090
1091 /**
1092 * Function for sorting Command structures based on timeStamp
1093 *
1094 * @param a Memory Command
1095 * @param next Memory Command
1096 * @return true if timeStamp of Command 1 < timeStamp of Command 2
1097 */
1098 static bool sortTime(const Command& cmd, const Command& cmd_next) {
1099 return cmd.timeStamp < cmd_next.timeStamp;
1100 };
1101
1102 public:
1103
1104 void regStats() override;
1105
1106 DRAMCtrl(const DRAMCtrlParams* p);
1107
1108 DrainState drain() override;
1109
1110 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
1111 PortID idx = InvalidPortID) override;
1112
1113 virtual void init() override;
1114 virtual void startup() override;
1115 virtual void drainResume() override;
1116
1117 /**
1118 * Return true once refresh is complete for all ranks and there are no
1119 * additional commands enqueued. (only evaluated when draining)
1120 * This will ensure that all banks are closed, power state is IDLE, and
1121 * power stats have been updated
1122 *
1123 * @return true if all ranks have refreshed, with no commands enqueued
1124 *
1125 */
1126 bool allRanksDrained() const;
1127
1128 protected:
1129
1130 Tick recvAtomic(PacketPtr pkt);
1131 void recvFunctional(PacketPtr pkt);
1132 bool recvTimingReq(PacketPtr pkt);
1133
1134};
1135
1136#endif //__MEM_DRAM_CTRL_HH__
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