dram_ctrl.hh (10618:bb665366cc00) | dram_ctrl.hh (10619:6dd27a0e0d23) |
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1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 107 unchanged lines hidden (view full) --- 116 117 /** 118 * Our incoming port, for a multi-ported controller add a crossbar 119 * in front of it 120 */ 121 MemoryPort port; 122 123 /** | 1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 107 unchanged lines hidden (view full) --- 116 117 /** 118 * Our incoming port, for a multi-ported controller add a crossbar 119 * in front of it 120 */ 121 MemoryPort port; 122 123 /** |
124 * Remeber if the memory system is in timing mode 125 */ 126 bool isTimingMode; 127 128 /** |
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124 * Remember if we have to retry a request when available. 125 */ 126 bool retryRdReq; 127 bool retryWrReq; 128 129 /** 130 * Bus state used to control the read/write switching and drive 131 * the scheduling of the next request. --- 203 unchanged lines hidden (view full) --- 335 * Kick off accounting for power and refresh states and 336 * schedule initial refresh. 337 * 338 * @param ref_tick Tick for first refresh 339 */ 340 void startup(Tick ref_tick); 341 342 /** | 129 * Remember if we have to retry a request when available. 130 */ 131 bool retryRdReq; 132 bool retryWrReq; 133 134 /** 135 * Bus state used to control the read/write switching and drive 136 * the scheduling of the next request. --- 203 unchanged lines hidden (view full) --- 340 * Kick off accounting for power and refresh states and 341 * schedule initial refresh. 342 * 343 * @param ref_tick Tick for first refresh 344 */ 345 void startup(Tick ref_tick); 346 347 /** |
348 * Stop the refresh events. 349 */ 350 void suspend(); 351 352 /** |
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343 * Check if the current rank is available for scheduling. 344 * 345 * @param Return true if the rank is idle from a refresh point of view 346 */ 347 bool isAvailable() const { return refreshState == REF_IDLE; } 348 349 /** 350 * Let the rank check if it was waiting for requests to drain --- 499 unchanged lines hidden (view full) --- 850 851 DRAMCtrl(const DRAMCtrlParams* p); 852 853 unsigned int drain(DrainManager* dm); 854 855 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 856 PortID idx = InvalidPortID); 857 | 353 * Check if the current rank is available for scheduling. 354 * 355 * @param Return true if the rank is idle from a refresh point of view 356 */ 357 bool isAvailable() const { return refreshState == REF_IDLE; } 358 359 /** 360 * Let the rank check if it was waiting for requests to drain --- 499 unchanged lines hidden (view full) --- 860 861 DRAMCtrl(const DRAMCtrlParams* p); 862 863 unsigned int drain(DrainManager* dm); 864 865 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 866 PortID idx = InvalidPortID); 867 |
858 virtual void init(); 859 virtual void startup(); | 868 virtual void init() M5_ATTR_OVERRIDE; 869 virtual void startup() M5_ATTR_OVERRIDE; 870 virtual void drainResume() M5_ATTR_OVERRIDE; |
860 861 protected: 862 863 Tick recvAtomic(PacketPtr pkt); 864 void recvFunctional(PacketPtr pkt); 865 bool recvTimingReq(PacketPtr pkt); 866 867}; 868 869#endif //__MEM_DRAM_CTRL_HH__ | 871 872 protected: 873 874 Tick recvAtomic(PacketPtr pkt); 875 void recvFunctional(PacketPtr pkt); 876 bool recvTimingReq(PacketPtr pkt); 877 878}; 879 880#endif //__MEM_DRAM_CTRL_HH__ |