1/*
2 * Copyright (c) 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
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37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 */
46
47/**
48 * @file
49 * DRAMCtrl declaration
50 */
51
52#ifndef __MEM_DRAM_CTRL_HH__
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82 * high performance, and lots of flexibility, allowing users to
83 * evaluate the system impact of a wide range of memory technologies,
84 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
85 *
86 * For more details, please see Hansson et al, "Simulating DRAM
87 * controllers for future system architecture exploration",
88 * Proc. ISPASS, 2014. If you use this model as part of your research
89 * please cite the paper.
90 */
91class DRAMCtrl : public AbstractMemory
92{
93
94 private:
95
96 // For now, make use of a queued slave port to avoid dealing with
97 // flow control for the responses being sent back
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135 bool retryWrReq;
136
137 /**
138 * Bus state used to control the read/write switching and drive
139 * the scheduling of the next request.
140 */
141 enum BusState {
142 READ = 0,
143 READ_TO_WRITE,
144 WRITE,
145 WRITE_TO_READ
146 };
147
148 BusState busState;
149
150 /**
151 * Simple structure to hold the values needed to keep track of
152 * commands for DRAMPower
153 */
154 struct Command {
155 Data::MemCommand::cmds type;
156 uint8_t bank;
157 Tick timeStamp;
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193 openRow(NO_ROW), bank(0), bankgr(0),
194 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
195 rowAccesses(0), bytesAccessed(0)
196 { }
197 };
198
199
200 /**
201 * Rank class includes a vector of banks. Refresh and Power state
202 * machines are defined per rank. Events required to change the
203 * state of the refresh and power state machine are scheduled per
204 * rank. This class allows the implementation of rank-wise refresh
205 * and rank-wise power-down.
206 */
207 class Rank : public EventManager
208 {
209
210 private:
211
212 /**
213 * The power state captures the different operational states of
214 * the DRAM and interacts with the bus read/write state machine,
215 * and the refresh state machine. In the idle state all banks are
216 * precharged. From there we either go to an auto refresh (as
217 * determined by the refresh state machine), or to a precharge
218 * power down mode. From idle the memory can also go to the active
219 * state (with one or more banks active), and in turn from there
220 * to active power down. At the moment we do not capture the deep
221 * power down and self-refresh state.
222 */
223 enum PowerState {
224 PWR_IDLE = 0,
225 PWR_REF,
226 PWR_PRE_PDN,
227 PWR_ACT,
228 PWR_ACT_PDN
229 };
230
231 /**
232 * The refresh state is used to control the progress of the
233 * refresh scheduling. When normal operation is in progress the
234 * refresh state is idle. From there, it progresses to the refresh
235 * drain state once tREFI has passed. The refresh drain state
236 * captures the DRAM row active state, as it will stay there until
237 * all ongoing accesses complete. Thereafter all banks are
238 * precharged, and lastly, the DRAM is refreshed.
239 */
240 enum RefreshState {
241 REF_IDLE = 0,
242 REF_DRAIN,
243 REF_PRE,
244 REF_RUN
245 };
246
247 /**
248 * A reference to the parent DRAMCtrl instance
249 */
250 DRAMCtrl& memory;
251
252 /**
253 * Since we are taking decisions out of order, we need to keep
254 * track of what power transition is happening at what time, such
255 * that we can go back in time and change history. For example, if
256 * we precharge all banks and schedule going to the idle state, we
257 * might at a later point decide to activate a bank before the
258 * transition to idle would have taken place.
259 */
260 PowerState pwrStateTrans;
261
262 /**
263 * Current power state.
264 */
265 PowerState pwrState;
266
267 /**
268 * Track when we transitioned to the current power state
269 */
270 Tick pwrStateTick;
271
272 /**
273 * current refresh state
274 */
275 RefreshState refreshState;
276
277 /**
278 * Keep track of when a refresh is due.
279 */
280 Tick refreshDueAt;
281
282 /*
283 * Command energies
284 */
285 Stats::Scalar actEnergy;
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293 */
294 Stats::Scalar actBackEnergy;
295
296 /*
297 * Precharge Background Energy
298 */
299 Stats::Scalar preBackEnergy;
300
301 Stats::Scalar totalEnergy;
302 Stats::Scalar averagePower;
303
304 /**
305 * Track time spent in each power state.
306 */
307 Stats::Vector pwrStateTime;
308
309 /**
310 * Function to update Power Stats
311 */
312 void updatePowerStats();
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318 * @param pwr_state Power state to transition to
319 * @param tick Tick when transition should take place
320 */
321 void schedulePowerEvent(PowerState pwr_state, Tick tick);
322
323 public:
324
325 /**
326 * Current Rank index
327 */
328 uint8_t rank;
329
330 /**
331 * One DRAMPower instance per rank
332 */
333 DRAMPower power;
334
335 /**
336 * List of comamnds issued, to be sent to DRAMPpower at refresh
337 * and stats dump. Keep commands here since commands to different
338 * banks are added out of order. Will only pass commands up to
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372
373 /**
374 * Stop the refresh events.
375 */
376 void suspend();
377
378 /**
379 * Check if the current rank is available for scheduling.
380 *
381 * @param Return true if the rank is idle from a refresh point of view
382 */
383 bool isAvailable() const { return refreshState == REF_IDLE; }
384
385 /**
386 * Check if the current rank has all banks closed and is not
387 * in a low power state
388 *
389 * @param Return true if the rank is idle from a bank
390 * and power point of view
391 */
392 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
393
394 /**
395 * Let the rank check if it was waiting for requests to drain
396 * to allow it to transition states.
397 */
398 void checkDrainDone();
399
400 /**
401 * Push command out of cmdList queue that are scheduled at
402 * or before curTick() to DRAMPower library
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410 */
411 void regStats();
412
413 /**
414 * Computes stats just prior to dump event
415 */
416 void computeStats();
417
418 void processActivateEvent();
419 EventWrapper<Rank, &Rank::processActivateEvent>
420 activateEvent;
421
422 void processPrechargeEvent();
423 EventWrapper<Rank, &Rank::processPrechargeEvent>
424 prechargeEvent;
425
426 void processRefreshEvent();
427 EventWrapper<Rank, &Rank::processRefreshEvent>
428 refreshEvent;
429
430 void processPowerEvent();
431 EventWrapper<Rank, &Rank::processPowerEvent>
432 powerEvent;
433
434 };
435
436 // define the process to compute stats on simulation exit
437 // defined per rank as the per rank stats are based on state
438 // transition and periodically updated, requiring re-sync at
439 // exit.
440 class RankDumpCallback : public Callback
441 {
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2 * Copyright (c) 2012-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 28 unchanged lines hidden (view full) ---
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Hansson
41 * Ani Udipi
42 * Neha Agarwal
43 * Omar Naji
44 * Matthias Jung
45 */
46
47/**
48 * @file
49 * DRAMCtrl declaration
50 */
51
52#ifndef __MEM_DRAM_CTRL_HH__
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82 * high performance, and lots of flexibility, allowing users to
83 * evaluate the system impact of a wide range of memory technologies,
84 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
85 *
86 * For more details, please see Hansson et al, "Simulating DRAM
87 * controllers for future system architecture exploration",
88 * Proc. ISPASS, 2014. If you use this model as part of your research
89 * please cite the paper.
90 */
91class DRAMCtrl : public AbstractMemory
92{
93
94 private:
95
96 // For now, make use of a queued slave port to avoid dealing with
97 // flow control for the responses being sent back
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135 bool retryWrReq;
136
137 /**
138 * Bus state used to control the read/write switching and drive
139 * the scheduling of the next request.
140 */
141 enum BusState {
142 READ = 0,
143 READ_TO_WRITE,
144 WRITE,
145 WRITE_TO_READ
146 };
147
148 BusState busState;
149
150 /**
151 * Simple structure to hold the values needed to keep track of
152 * commands for DRAMPower
153 */
154 struct Command {
155 Data::MemCommand::cmds type;
156 uint8_t bank;
157 Tick timeStamp;
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193 openRow(NO_ROW), bank(0), bankgr(0),
194 colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
195 rowAccesses(0), bytesAccessed(0)
196 { }
197 };
198
199
200 /**
201 * Rank class includes a vector of banks. Refresh and Power state
202 * machines are defined per rank. Events required to change the
203 * state of the refresh and power state machine are scheduled per
204 * rank. This class allows the implementation of rank-wise refresh
205 * and rank-wise power-down.
206 */
207 class Rank : public EventManager
208 {
209
210 private:
211
212 /**
213 * The power state captures the different operational states of
214 * the DRAM and interacts with the bus read/write state machine,
215 * and the refresh state machine. In the idle state all banks are
216 * precharged. From there we either go to an auto refresh (as
217 * determined by the refresh state machine), or to a precharge
218 * power down mode. From idle the memory can also go to the active
219 * state (with one or more banks active), and in turn from there
220 * to active power down. At the moment we do not capture the deep
221 * power down and self-refresh state.
222 */
223 enum PowerState {
224 PWR_IDLE = 0,
225 PWR_REF,
226 PWR_PRE_PDN,
227 PWR_ACT,
228 PWR_ACT_PDN
229 };
230
231 /**
232 * The refresh state is used to control the progress of the
233 * refresh scheduling. When normal operation is in progress the
234 * refresh state is idle. From there, it progresses to the refresh
235 * drain state once tREFI has passed. The refresh drain state
236 * captures the DRAM row active state, as it will stay there until
237 * all ongoing accesses complete. Thereafter all banks are
238 * precharged, and lastly, the DRAM is refreshed.
239 */
240 enum RefreshState {
241 REF_IDLE = 0,
242 REF_DRAIN,
243 REF_PRE,
244 REF_RUN
245 };
246
247 /**
248 * A reference to the parent DRAMCtrl instance
249 */
250 DRAMCtrl& memory;
251
252 /**
253 * Since we are taking decisions out of order, we need to keep
254 * track of what power transition is happening at what time, such
255 * that we can go back in time and change history. For example, if
256 * we precharge all banks and schedule going to the idle state, we
257 * might at a later point decide to activate a bank before the
258 * transition to idle would have taken place.
259 */
260 PowerState pwrStateTrans;
261
262 /**
263 * Current power state.
264 */
265 PowerState pwrState;
266
267 /**
268 * Track when we transitioned to the current power state
269 */
270 Tick pwrStateTick;
271
272 /**
273 * current refresh state
274 */
275 RefreshState refreshState;
276
277 /**
278 * Keep track of when a refresh is due.
279 */
280 Tick refreshDueAt;
281
282 /*
283 * Command energies
284 */
285 Stats::Scalar actEnergy;
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293 */
294 Stats::Scalar actBackEnergy;
295
296 /*
297 * Precharge Background Energy
298 */
299 Stats::Scalar preBackEnergy;
300
301 Stats::Scalar totalEnergy;
302 Stats::Scalar averagePower;
303
304 /**
305 * Track time spent in each power state.
306 */
307 Stats::Vector pwrStateTime;
308
309 /**
310 * Function to update Power Stats
311 */
312 void updatePowerStats();
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318 * @param pwr_state Power state to transition to
319 * @param tick Tick when transition should take place
320 */
321 void schedulePowerEvent(PowerState pwr_state, Tick tick);
322
323 public:
324
325 /**
326 * Current Rank index
327 */
328 uint8_t rank;
329
330 /**
331 * One DRAMPower instance per rank
332 */
333 DRAMPower power;
334
335 /**
336 * List of comamnds issued, to be sent to DRAMPpower at refresh
337 * and stats dump. Keep commands here since commands to different
338 * banks are added out of order. Will only pass commands up to
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372
373 /**
374 * Stop the refresh events.
375 */
376 void suspend();
377
378 /**
379 * Check if the current rank is available for scheduling.
380 *
381 * @param Return true if the rank is idle from a refresh point of view
382 */
383 bool isAvailable() const { return refreshState == REF_IDLE; }
384
385 /**
386 * Check if the current rank has all banks closed and is not
387 * in a low power state
388 *
389 * @param Return true if the rank is idle from a bank
390 * and power point of view
391 */
392 bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
393
394 /**
395 * Let the rank check if it was waiting for requests to drain
396 * to allow it to transition states.
397 */
398 void checkDrainDone();
399
400 /**
401 * Push command out of cmdList queue that are scheduled at
402 * or before curTick() to DRAMPower library
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410 */
411 void regStats();
412
413 /**
414 * Computes stats just prior to dump event
415 */
416 void computeStats();
417
418 void processActivateEvent();
419 EventWrapper<Rank, &Rank::processActivateEvent>
420 activateEvent;
421
422 void processPrechargeEvent();
423 EventWrapper<Rank, &Rank::processPrechargeEvent>
424 prechargeEvent;
425
426 void processRefreshEvent();
427 EventWrapper<Rank, &Rank::processRefreshEvent>
428 refreshEvent;
429
430 void processPowerEvent();
431 EventWrapper<Rank, &Rank::processPowerEvent>
432 powerEvent;
433
434 };
435
436 // define the process to compute stats on simulation exit
437 // defined per rank as the per rank stats are based on state
438 // transition and periodically updated, requiring re-sync at
439 // exit.
440 class RankDumpCallback : public Callback
441 {
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