1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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116
117 /**
118 * Our incoming port, for a multi-ported controller add a crossbar
119 * in front of it
120 */
121 MemoryPort port;
122
123 /**
124 * Remember if we have to retry a request when available.
125 */
126 bool retryRdReq;
127 bool retryWrReq;
128
129 /**
130 * Bus state used to control the read/write switching and drive
131 * the scheduling of the next request.

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335 * Kick off accounting for power and refresh states and
336 * schedule initial refresh.
337 *
338 * @param ref_tick Tick for first refresh
339 */
340 void startup(Tick ref_tick);
341
342 /**
343 * Check if the current rank is available for scheduling.
344 *
345 * @param Return true if the rank is idle from a refresh point of view
346 */
347 bool isAvailable() const { return refreshState == REF_IDLE; }
348
349 /**
350 * Let the rank check if it was waiting for requests to drain

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850
851 DRAMCtrl(const DRAMCtrlParams* p);
852
853 unsigned int drain(DrainManager* dm);
854
855 virtual BaseSlavePort& getSlavePort(const std::string& if_name,
856 PortID idx = InvalidPortID);
857
858 virtual void init();
859 virtual void startup();
860
861 protected:
862
863 Tick recvAtomic(PacketPtr pkt);
864 void recvFunctional(PacketPtr pkt);
865 bool recvTimingReq(PacketPtr pkt);
866
867};
868
869#endif //__MEM_DRAM_CTRL_HH__