1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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255 };
256
257 /**
258 * Bunch of things requires to setup "events" in gem5
259 * When event "respondEvent" occurs for example, the method
260 * processRespondEvent is called; no parameters are allowed
261 * in these methods
262 */
263 void processRespondEvent();
264 EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
265
266 void processRefreshEvent();
267 EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
268
269 void processNextReqEvent();
270 EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
271
272
273 /**
274 * Check if the read queue has room for more entries
275 *
276 * @param pktCount The number of entries needed in the read queue
277 * @return true if read queue is full, false otherwise
278 */
279 bool readQueueFull(unsigned int pktCount) const;
280

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544 REF_IDLE = 0,
545 REF_DRAIN,
546 REF_PRE,
547 REF_RUN
548 };
549
550 RefreshState refreshState;
551
552 Tick prevArrival;
553
554 /**
555 * The soonest you have to start thinking about the next request
556 * is the longest access time that can occur before
557 * busBusyUntil. Assuming you need to precharge, open a new row,
558 * and access, it is tRP + tRCD + tCL.
559 */

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615 Stats::Scalar readRowHits;
616 Stats::Scalar writeRowHits;
617 Stats::Formula readRowHitRate;
618 Stats::Formula writeRowHitRate;
619 Stats::Formula avgGap;
620
621 // DRAM Power Calculation
622 Stats::Formula pageHitRate;
623 Stats::Formula prechargeAllPercent;
624 Stats::Scalar prechargeAllTime;
625
626 // To track number of cycles the DRAM is idle, i.e. all the banks
627 // are precharged
628 Tick idleStartTick;
629
630 // To track number of banks which are currently active
631 unsigned int numBanksActive;
632
633 /** @todo this is a temporary workaround until the 4-phase code is
634 * committed. upstream caches needs this packet until true is returned, so
635 * hold onto it for deletion until a subsequent call
636 */

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