1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
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57#include "enums/MemSched.hh"
58#include "enums/PageManage.hh"
59#include "mem/abstract_mem.hh"
60#include "mem/qport.hh"
61#include "params/DRAMCtrl.hh"
62#include "sim/eventq.hh"
63
64/**
65 * The DRAM controller is a single-channel memory controller capturing
66 * the most important timing constraints associated with a
67 * contemporary DRAM. For multi-channel memory systems, the controller
68 * is combined with a crossbar model, with the channel address
69 * interleaving taking part in the crossbar.
70 *
71 * As a basic design principle, this controller
72 * model is not cycle callable, but instead uses events to: 1) decide
73 * when new decisions can be made, 2) when resources become available,
74 * 3) when things are to be considered done, and 4) when to send
75 * things back. Through these simple principles, the model delivers
76 * high performance, and lots of flexibility, allowing users to
77 * evaluate the system impact of a wide range of memory technologies,
78 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
79 *
80 * For more details, please see Hansson et al, "Simulating DRAM
81 * controllers for future system architecture exploration",
82 * Proc. ISPASS, 2014. If you use this model as part of your research
83 * please cite the paper.
84 */
85class DRAMCtrl : public AbstractMemory
86{
87
88 private:
89
90 // For now, make use of a queued slave port to avoid dealing with
91 // flow control for the responses being sent back
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2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 48 unchanged lines hidden (view full) ---
57#include "enums/MemSched.hh"
58#include "enums/PageManage.hh"
59#include "mem/abstract_mem.hh"
60#include "mem/qport.hh"
61#include "params/DRAMCtrl.hh"
62#include "sim/eventq.hh"
63
64/**
65 * The DRAM controller is a single-channel memory controller capturing
66 * the most important timing constraints associated with a
67 * contemporary DRAM. For multi-channel memory systems, the controller
68 * is combined with a crossbar model, with the channel address
69 * interleaving taking part in the crossbar.
70 *
71 * As a basic design principle, this controller
72 * model is not cycle callable, but instead uses events to: 1) decide
73 * when new decisions can be made, 2) when resources become available,
74 * 3) when things are to be considered done, and 4) when to send
75 * things back. Through these simple principles, the model delivers
76 * high performance, and lots of flexibility, allowing users to
77 * evaluate the system impact of a wide range of memory technologies,
78 * such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
79 *
80 * For more details, please see Hansson et al, "Simulating DRAM
81 * controllers for future system architecture exploration",
82 * Proc. ISPASS, 2014. If you use this model as part of your research
83 * please cite the paper.
84 */
85class DRAMCtrl : public AbstractMemory
86{
87
88 private:
89
90 // For now, make use of a queued slave port to avoid dealing with
91 // flow control for the responses being sent back
--- 604 unchanged lines hidden ---