dram_ctrl.cc (11846:b9436a4bbbb9) dram_ctrl.cc (12081:cb5fe81fd522)
1/*
2 * Copyright (c) 2010-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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99 // address decoding
100 fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not "
101 "allowed, must be a power of two\n", ranksPerChannel);
102
103 fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, "
104 "must be a power of two\n", burstSize);
105
106 for (int i = 0; i < ranksPerChannel; i++) {
1/*
2 * Copyright (c) 2010-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 90 unchanged lines hidden (view full) ---

99 // address decoding
100 fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not "
101 "allowed, must be a power of two\n", ranksPerChannel);
102
103 fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, "
104 "must be a power of two\n", burstSize);
105
106 for (int i = 0; i < ranksPerChannel; i++) {
107 Rank* rank = new Rank(*this, p);
107 Rank* rank = new Rank(*this, p, i);
108 ranks.push_back(rank);
108 ranks.push_back(rank);
109
110 rank->actTicks.resize(activationLimit, 0);
111 rank->banks.resize(banksPerRank);
112 rank->rank = i;
113
114 for (int b = 0; b < banksPerRank; b++) {
115 rank->banks[b].bank = b;
116 // GDDR addressing of banks to BG is linear.
117 // Here we assume that all DRAM generations address bank groups as
118 // follows:
119 if (bankGroupArch) {
120 // Simply assign lower bits to bank group in order to
121 // rotate across bank groups as banks are incremented
122 // e.g. with 4 banks per bank group and 16 banks total:
123 // banks 0,4,8,12 are in bank group 0
124 // banks 1,5,9,13 are in bank group 1
125 // banks 2,6,10,14 are in bank group 2
126 // banks 3,7,11,15 are in bank group 3
127 rank->banks[b].bankgr = b % bankGroupsPerRank;
128 } else {
129 // No bank groups; simply assign to bank number
130 rank->banks[b].bankgr = b;
131 }
132 }
133 }
134
135 // perform a basic check of the write thresholds
136 if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
137 fatal("Write buffer low threshold %d must be smaller than the "
138 "high threshold %d\n", p->write_low_thresh_perc,
139 p->write_high_thresh_perc);
140

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1621 }
1622 }
1623 }
1624 }
1625
1626 return make_pair(bank_mask, hidden_bank_prep);
1627}
1628
109 }
110
111 // perform a basic check of the write thresholds
112 if (p->write_low_thresh_perc >= p->write_high_thresh_perc)
113 fatal("Write buffer low threshold %d must be smaller than the "
114 "high threshold %d\n", p->write_low_thresh_perc,
115 p->write_high_thresh_perc);
116

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1597 }
1598 }
1599 }
1600 }
1601
1602 return make_pair(bank_mask, hidden_bank_prep);
1603}
1604
1629DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p)
1605DRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank)
1630 : EventManager(&_memory), memory(_memory),
1631 pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE),
1632 pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE),
1606 : EventManager(&_memory), memory(_memory),
1607 pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE),
1608 pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE),
1633 refreshState(REF_IDLE), inLowPowerState(false), rank(0),
1609 refreshState(REF_IDLE), inLowPowerState(false), rank(rank),
1634 readEntries(0), writeEntries(0), outstandingEvents(0),
1610 readEntries(0), writeEntries(0), outstandingEvents(0),
1635 wakeUpAllowedAt(0), power(_p, false), numBanksActive(0),
1611 wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank),
1612 numBanksActive(0), actTicks(_p->activation_limit, 0),
1636 writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
1637 refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
1613 writeDoneEvent(*this), activateEvent(*this), prechargeEvent(*this),
1614 refreshEvent(*this), powerEvent(*this), wakeUpEvent(*this)
1638{ }
1615{
1616 for (int b = 0; b < _p->banks_per_rank; b++) {
1617 banks[b].bank = b;
1618 // GDDR addressing of banks to BG is linear.
1619 // Here we assume that all DRAM generations address bank groups as
1620 // follows:
1621 if (_p->bank_groups_per_rank > 0) {
1622 // Simply assign lower bits to bank group in order to
1623 // rotate across bank groups as banks are incremented
1624 // e.g. with 4 banks per bank group and 16 banks total:
1625 // banks 0,4,8,12 are in bank group 0
1626 // banks 1,5,9,13 are in bank group 1
1627 // banks 2,6,10,14 are in bank group 2
1628 // banks 3,7,11,15 are in bank group 3
1629 banks[b].bankgr = b % _p->bank_groups_per_rank;
1630 } else {
1631 // No bank groups; simply assign to bank number
1632 banks[b].bankgr = b;
1633 }
1634 }
1635}
1639
1640void
1641DRAMCtrl::Rank::startup(Tick ref_tick)
1642{
1643 assert(ref_tick > curTick());
1644
1645 pwrStateTick = curTick();
1646

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1637void
1638DRAMCtrl::Rank::startup(Tick ref_tick)
1639{
1640 assert(ref_tick > curTick());
1641
1642 pwrStateTick = curTick();
1643

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