dram_ctrl.cc (11673:9f3ccf96bb5a) dram_ctrl.cc (11675:60d18201148d)
1/*
1/*
2 * Copyright (c) 2010-2015 ARM Limited
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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893
894 ++rank_ref.numBanksActive;
895 assert(rank_ref.numBanksActive <= banksPerRank);
896
897 DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
898 bank_ref.bank, rank_ref.rank, act_tick,
899 ranks[rank_ref.rank]->numBanksActive);
900
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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893
894 ++rank_ref.numBanksActive;
895 assert(rank_ref.numBanksActive <= banksPerRank);
896
897 DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n",
898 bank_ref.bank, rank_ref.rank, act_tick,
899 ranks[rank_ref.rank]->numBanksActive);
900
901 rank_ref.power.powerlib.doCommand(MemCommand::ACT, bank_ref.bank,
902 divCeil(act_tick, tCK) -
903 timeStampOffset);
901 rank_ref.cmdList.push_back(Command(MemCommand::ACT, bank_ref.bank,
902 act_tick));
904
905 DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) -
906 timeStampOffset, bank_ref.bank, rank_ref.rank);
907
908 // The next access has to respect tRAS for this bank
909 bank_ref.preAllowedAt = act_tick + tRAS;
910
911 // Respect the row-to-column command delay

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997 --rank_ref.numBanksActive;
998
999 DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got "
1000 "%d active\n", bank.bank, rank_ref.rank, pre_at,
1001 rank_ref.numBanksActive);
1002
1003 if (trace) {
1004
903
904 DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) -
905 timeStampOffset, bank_ref.bank, rank_ref.rank);
906
907 // The next access has to respect tRAS for this bank
908 bank_ref.preAllowedAt = act_tick + tRAS;
909
910 // Respect the row-to-column command delay

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996 --rank_ref.numBanksActive;
997
998 DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got "
999 "%d active\n", bank.bank, rank_ref.rank, pre_at,
1000 rank_ref.numBanksActive);
1001
1002 if (trace) {
1003
1005 rank_ref.power.powerlib.doCommand(MemCommand::PRE, bank.bank,
1006 divCeil(pre_at, tCK) -
1007 timeStampOffset);
1004 rank_ref.cmdList.push_back(Command(MemCommand::PRE, bank.bank,
1005 pre_at));
1008 DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) -
1009 timeStampOffset, bank.bank, rank_ref.rank);
1010 }
1011 // if we look at the current number of active banks we might be
1012 // tempted to think the DRAM is now idle, however this can be
1013 // undone by an activate that is scheduled to happen before we
1014 // would have reached the idle state, so schedule an event and
1015 // rather check once we actually make it to the point in time when

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1171
1172 // DRAMPower trace command to be written
1173 std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR";
1174
1175 // MemCommand required for DRAMPower library
1176 MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD :
1177 MemCommand::WR;
1178
1006 DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) -
1007 timeStampOffset, bank.bank, rank_ref.rank);
1008 }
1009 // if we look at the current number of active banks we might be
1010 // tempted to think the DRAM is now idle, however this can be
1011 // undone by an activate that is scheduled to happen before we
1012 // would have reached the idle state, so schedule an event and
1013 // rather check once we actually make it to the point in time when

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1169
1170 // DRAMPower trace command to be written
1171 std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR";
1172
1173 // MemCommand required for DRAMPower library
1174 MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD :
1175 MemCommand::WR;
1176
1179 // if this access should use auto-precharge, then we are
1180 // closing the row
1181 if (auto_precharge) {
1182 // if auto-precharge push a PRE command at the correct tick to the
1183 // list used by DRAMPower library to calculate power
1184 prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt));
1185
1186 DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
1187 }
1188
1189 // Update bus state
1190 busBusyUntil = dram_pkt->readyTime;
1191
1192 DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n",
1193 dram_pkt->addr, dram_pkt->readyTime, busBusyUntil);
1194
1177 // Update bus state
1178 busBusyUntil = dram_pkt->readyTime;
1179
1180 DPRINTF(DRAM, "Access to %lld, ready at %lld bus busy until %lld.\n",
1181 dram_pkt->addr, dram_pkt->readyTime, busBusyUntil);
1182
1195 dram_pkt->rankRef.power.powerlib.doCommand(command, dram_pkt->bank,
1196 divCeil(cmd_at, tCK) -
1197 timeStampOffset);
1183 dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank,
1184 cmd_at));
1198
1199 DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) -
1200 timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank);
1201
1185
1186 DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) -
1187 timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank);
1188
1189 // if this access should use auto-precharge, then we are
1190 // closing the row after the read/write burst
1191 if (auto_precharge) {
1192 // if auto-precharge push a PRE command at the correct tick to the
1193 // list used by DRAMPower library to calculate power
1194 prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt));
1195
1196 DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId);
1197 }
1198
1202 // Update the minimum timing between the requests, this is a
1203 // conservative estimate of when we have to schedule the next
1204 // request to not introduce any unecessary bubbles. In most cases
1205 // we will wake up sooner than we have to.
1206 nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
1207
1208 // Update the stats and schedule the next request
1209 if (dram_pkt->isRead) {

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1554 refreshState = REF_PRE;
1555
1556 // hand control back to the refresh event loop
1557 schedule(refreshEvent, curTick());
1558 }
1559}
1560
1561void
1199 // Update the minimum timing between the requests, this is a
1200 // conservative estimate of when we have to schedule the next
1201 // request to not introduce any unecessary bubbles. In most cases
1202 // we will wake up sooner than we have to.
1203 nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
1204
1205 // Update the stats and schedule the next request
1206 if (dram_pkt->isRead) {

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1551 refreshState = REF_PRE;
1552
1553 // hand control back to the refresh event loop
1554 schedule(refreshEvent, curTick());
1555 }
1556}
1557
1558void
1559DRAMCtrl::Rank::flushCmdList()
1560{
1561 // at the moment sort the list of commands and update the counters
1562 // for DRAMPower libray when doing a refresh
1563 sort(cmdList.begin(), cmdList.end(), DRAMCtrl::sortTime);
1564
1565 auto next_iter = cmdList.begin();
1566 // push to commands to DRAMPower
1567 for ( ; next_iter != cmdList.end() ; ++next_iter) {
1568 Command cmd = *next_iter;
1569 if (cmd.timeStamp <= curTick()) {
1570 // Move all commands at or before curTick to DRAMPower
1571 power.powerlib.doCommand(cmd.type, cmd.bank,
1572 divCeil(cmd.timeStamp, memory.tCK) -
1573 memory.timeStampOffset);
1574 } else {
1575 // done - found all commands at or before curTick()
1576 // next_iter references the 1st command after curTick
1577 break;
1578 }
1579 }
1580 // reset cmdList to only contain commands after curTick
1581 // if there are no commands after curTick, updated cmdList will be empty
1582 // in this case, next_iter is cmdList.end()
1583 cmdList.assign(next_iter, cmdList.end());
1584}
1585
1586void
1562DRAMCtrl::Rank::processActivateEvent()
1563{
1564 // we should transition to the active state as soon as any bank is active
1565 if (pwrState != PWR_ACT)
1566 // note that at this point numBanksActive could be back at
1567 // zero again due to a precharge scheduled in the future
1568 schedulePowerEvent(PWR_ACT, curTick());
1569}

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1640 memory.prechargeBank(*this, b, pre_at, false);
1641 } else {
1642 b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at);
1643 b.preAllowedAt = std::max(b.preAllowedAt, pre_at);
1644 }
1645 }
1646
1647 // precharge all banks in rank
1587DRAMCtrl::Rank::processActivateEvent()
1588{
1589 // we should transition to the active state as soon as any bank is active
1590 if (pwrState != PWR_ACT)
1591 // note that at this point numBanksActive could be back at
1592 // zero again due to a precharge scheduled in the future
1593 schedulePowerEvent(PWR_ACT, curTick());
1594}

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1665 memory.prechargeBank(*this, b, pre_at, false);
1666 } else {
1667 b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at);
1668 b.preAllowedAt = std::max(b.preAllowedAt, pre_at);
1669 }
1670 }
1671
1672 // precharge all banks in rank
1648 power.powerlib.doCommand(MemCommand::PREA, 0,
1649 divCeil(pre_at, memory.tCK) -
1650 memory.timeStampOffset);
1673 cmdList.push_back(Command(MemCommand::PREA, 0, pre_at));
1651
1652 DPRINTF(DRAMPower, "%llu,PREA,0,%d\n",
1653 divCeil(pre_at, memory.tCK) -
1654 memory.timeStampOffset, rank);
1655 } else {
1656 DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
1657
1658 // go ahead and kick the power state machine into gear if

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1678
1679 Tick ref_done_at = curTick() + memory.tRFC;
1680
1681 for (auto &b : banks) {
1682 b.actAllowedAt = ref_done_at;
1683 }
1684
1685 // at the moment this affects all ranks
1674
1675 DPRINTF(DRAMPower, "%llu,PREA,0,%d\n",
1676 divCeil(pre_at, memory.tCK) -
1677 memory.timeStampOffset, rank);
1678 } else {
1679 DPRINTF(DRAM, "All banks already precharged, starting refresh\n");
1680
1681 // go ahead and kick the power state machine into gear if

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1701
1702 Tick ref_done_at = curTick() + memory.tRFC;
1703
1704 for (auto &b : banks) {
1705 b.actAllowedAt = ref_done_at;
1706 }
1707
1708 // at the moment this affects all ranks
1686 power.powerlib.doCommand(MemCommand::REF, 0,
1687 divCeil(curTick(), memory.tCK) -
1688 memory.timeStampOffset);
1709 cmdList.push_back(Command(MemCommand::REF, 0, curTick()));
1689
1710
1690 // at the moment sort the list of commands and update the counters
1691 // for DRAMPower libray when doing a refresh
1692 sort(power.powerlib.cmdList.begin(),
1693 power.powerlib.cmdList.end(), DRAMCtrl::sortTime);
1711 // All commands up to refresh have completed
1712 // flush cmdList to DRAMPower
1713 flushCmdList();
1694
1695 // update the counters for DRAMPower, passing false to
1696 // indicate that this is not the last command in the
1697 // list. DRAMPower requires this information for the
1698 // correct calculation of the background energy at the end
1699 // of the simulation. Ideally we would want to call this
1700 // function with true once at the end of the
1701 // simulation. However, the discarded energy is extremly

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1715 // update the counters for DRAMPower, passing false to
1716 // indicate that this is not the last command in the
1717 // list. DRAMPower requires this information for the
1718 // correct calculation of the background energy at the end
1719 // of the simulation. Ideally we would want to call this
1720 // function with true once at the end of the
1721 // simulation. However, the discarded energy is extremly

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