dram_ctrl.cc (11321:02e930db812d) dram_ctrl.cc (11334:9bd2e84abdca)
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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268 }
269}
270
271Tick
272DRAMCtrl::recvAtomic(PacketPtr pkt)
273{
274 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
275
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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268 }
269}
270
271Tick
272DRAMCtrl::recvAtomic(PacketPtr pkt)
273{
274 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
275
276 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
277 "is responding");
278
276 // do the actual memory access and turn the packet into a response
277 access(pkt);
278
279 Tick latency = 0;
279 // do the actual memory access and turn the packet into a response
280 access(pkt);
281
282 Tick latency = 0;
280 if (!pkt->cacheResponding() && pkt->hasData()) {
283 if (pkt->hasData()) {
281 // this value is not supposed to be accurate, just enough to
282 // keep things going, mimic a closed page
283 latency = tRP + tRCD + tCL;
284 }
285 return latency;
286}
287
288bool

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585
586bool
587DRAMCtrl::recvTimingReq(PacketPtr pkt)
588{
589 // This is where we enter from the outside world
590 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
591 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
592
284 // this value is not supposed to be accurate, just enough to
285 // keep things going, mimic a closed page
286 latency = tRP + tRCD + tCL;
287 }
288 return latency;
289}
290
291bool

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588
589bool
590DRAMCtrl::recvTimingReq(PacketPtr pkt)
591{
592 // This is where we enter from the outside world
593 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
594 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
595
593 // if a cache is responding, sink the packet without further action
594 if (pkt->cacheResponding()) {
595 pendingDelete.reset(pkt);
596 return true;
597 }
596 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
597 "is responding");
598
598
599 panic_if(!(pkt->isRead() || pkt->isWrite()),
600 "Should only see read and writes at memory controller\n");
601
599 // Calc avg gap between requests
600 if (prevArrival != 0) {
601 totGap += curTick() - prevArrival;
602 }
603 prevArrival = curTick();
604
605
606 // Find out how many dram packets a pkt translates to

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620 retryRdReq = true;
621 numRdRetry++;
622 return false;
623 } else {
624 addToReadQueue(pkt, dram_pkt_count);
625 readReqs++;
626 bytesReadSys += size;
627 }
602 // Calc avg gap between requests
603 if (prevArrival != 0) {
604 totGap += curTick() - prevArrival;
605 }
606 prevArrival = curTick();
607
608
609 // Find out how many dram packets a pkt translates to

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623 retryRdReq = true;
624 numRdRetry++;
625 return false;
626 } else {
627 addToReadQueue(pkt, dram_pkt_count);
628 readReqs++;
629 bytesReadSys += size;
630 }
628 } else if (pkt->isWrite()) {
631 } else {
632 assert(pkt->isWrite());
629 assert(size != 0);
630 if (writeQueueFull(dram_pkt_count)) {
631 DPRINTF(DRAM, "Write queue full, not accepting\n");
632 // remember that we have to retry this port
633 retryWrReq = true;
634 numWrRetry++;
635 return false;
636 } else {
637 addToWriteQueue(pkt, dram_pkt_count);
638 writeReqs++;
639 bytesWrittenSys += size;
640 }
633 assert(size != 0);
634 if (writeQueueFull(dram_pkt_count)) {
635 DPRINTF(DRAM, "Write queue full, not accepting\n");
636 // remember that we have to retry this port
637 retryWrReq = true;
638 numWrRetry++;
639 return false;
640 } else {
641 addToWriteQueue(pkt, dram_pkt_count);
642 writeReqs++;
643 bytesWrittenSys += size;
644 }
641 } else {
642 DPRINTF(DRAM,"Neither read nor write, ignore timing\n");
643 neitherReadNorWrite++;
644 accessAndRespond(pkt, 1);
645 }
646
647 return true;
648}
649
650void
651DRAMCtrl::processRespondEvent()
652{

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646
647 return true;
648}
649
650void
651DRAMCtrl::processRespondEvent()
652{

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