dram_ctrl.cc (11194:c3ba89c653a9) dram_ctrl.cc (11284:b3926db25371)
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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272DRAMCtrl::recvAtomic(PacketPtr pkt)
273{
274 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
275
276 // do the actual memory access and turn the packet into a response
277 access(pkt);
278
279 Tick latency = 0;
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 263 unchanged lines hidden (view full) ---

272DRAMCtrl::recvAtomic(PacketPtr pkt)
273{
274 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
275
276 // do the actual memory access and turn the packet into a response
277 access(pkt);
278
279 Tick latency = 0;
280 if (!pkt->memInhibitAsserted() && pkt->hasData()) {
280 if (!pkt->cacheResponding() && pkt->hasData()) {
281 // this value is not supposed to be accurate, just enough to
282 // keep things going, mimic a closed page
283 latency = tRP + tRCD + tCL;
284 }
285 return latency;
286}
287
288bool

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585
586bool
587DRAMCtrl::recvTimingReq(PacketPtr pkt)
588{
589 // This is where we enter from the outside world
590 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
591 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
592
281 // this value is not supposed to be accurate, just enough to
282 // keep things going, mimic a closed page
283 latency = tRP + tRCD + tCL;
284 }
285 return latency;
286}
287
288bool

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585
586bool
587DRAMCtrl::recvTimingReq(PacketPtr pkt)
588{
589 // This is where we enter from the outside world
590 DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n",
591 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
592
593 // sink inhibited packets without further action
594 if (pkt->memInhibitAsserted()) {
593 // if a cache is responding, sink the packet without further action
594 if (pkt->cacheResponding()) {
595 pendingDelete.reset(pkt);
596 return true;
597 }
598
599 // Calc avg gap between requests
600 if (prevArrival != 0) {
601 totGap += curTick() - prevArrival;
602 }

--- 1642 unchanged lines hidden --- 		595 pendingDelete.reset(pkt);
596 return true;
597 }
598
599 // Calc avg gap between requests
600 if (prevArrival != 0) {
601 totGap += curTick() - prevArrival;
602 }

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