dram_ctrl.cc (10620:74834c49fbbe) dram_ctrl.cc (10646:17d8d0a624a0)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64 drainManager(NULL),
65 deviceSize(p->device_size),
66 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
67 deviceRowBufferSize(p->device_rowbuffer_size),
68 devicesPerRank(p->devices_per_rank),
69 burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
70 rowBufferSize(devicesPerRank * deviceRowBufferSize),
71 columnsPerRowBuffer(rowBufferSize / burstSize),
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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64 drainManager(NULL),
65 deviceSize(p->device_size),
66 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
67 deviceRowBufferSize(p->device_rowbuffer_size),
68 devicesPerRank(p->devices_per_rank),
69 burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8),
70 rowBufferSize(devicesPerRank * deviceRowBufferSize),
71 columnsPerRowBuffer(rowBufferSize / burstSize),
72 columnsPerStripe(range.granularity() / burstSize),
72 columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1),
73 ranksPerChannel(p->ranks_per_channel),
74 bankGroupsPerRank(p->bank_groups_per_rank),
75 bankGroupArch(p->bank_groups_per_rank > 0),
76 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
77 readBufferSize(p->read_buffer_size),
78 writeBufferSize(p->write_buffer_size),
79 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
80 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),

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148 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
149 AbstractMemory::size());
150
151 DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n",
152 rowBufferSize, columnsPerRowBuffer);
153
154 rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel);
155
73 ranksPerChannel(p->ranks_per_channel),
74 bankGroupsPerRank(p->bank_groups_per_rank),
75 bankGroupArch(p->bank_groups_per_rank > 0),
76 banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0),
77 readBufferSize(p->read_buffer_size),
78 writeBufferSize(p->write_buffer_size),
79 writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0),
80 writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),

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148 DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
149 AbstractMemory::size());
150
151 DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n",
152 rowBufferSize, columnsPerRowBuffer);
153
154 rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel);
155
156 // a bit of sanity checks on the interleaving
157 if (range.interleaved()) {
158 if (channels != range.stripes())
159 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
160 name(), range.stripes(), channels);
161
162 if (addrMapping == Enums::RoRaBaChCo) {
163 if (rowBufferSize != range.granularity()) {
164 fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
165 "address map\n", name());
166 }
167 } else if (addrMapping == Enums::RoRaBaCoCh ||
168 addrMapping == Enums::RoCoRaBaCh) {
169 // for the interleavings with channel bits in the bottom,
170 // if the system uses a channel striping granularity that
171 // is larger than the DRAM burst size, then map the
172 // sequential accesses within a stripe to a number of
173 // columns in the DRAM, effectively placing some of the
174 // lower-order column bits as the least-significant bits
175 // of the address (above the ones denoting the burst size)
176 assert(columnsPerStripe >= 1);
177
178 // channel striping has to be done at a granularity that
179 // is equal or larger to a cache line
180 if (system()->cacheLineSize() > range.granularity()) {
181 fatal("Channel interleaving of %s must be at least as large "
182 "as the cache line size\n", name());
183 }
184
185 // ...and equal or smaller than the row-buffer size
186 if (rowBufferSize < range.granularity()) {
187 fatal("Channel interleaving of %s must be at most as large "
188 "as the row-buffer size\n", name());
189 }
190 // this is essentially the check above, so just to be sure
191 assert(columnsPerStripe <= columnsPerRowBuffer);
192 }
193 }
194
195 // some basic sanity checks
196 if (tREFI <= tRP || tREFI <= tRFC) {
197 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
198 tREFI, tRP, tRFC);
199 }
200
201 // basic bank group architecture checks ->
202 if (bankGroupArch) {

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234{
235 AbstractMemory::init();
236
237 if (!port.isConnected()) {
238 fatal("DRAMCtrl %s is unconnected!\n", name());
239 } else {
240 port.sendRangeChange();
241 }
156 // some basic sanity checks
157 if (tREFI <= tRP || tREFI <= tRFC) {
158 fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n",
159 tREFI, tRP, tRFC);
160 }
161
162 // basic bank group architecture checks ->
163 if (bankGroupArch) {

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195{
196 AbstractMemory::init();
197
198 if (!port.isConnected()) {
199 fatal("DRAMCtrl %s is unconnected!\n", name());
200 } else {
201 port.sendRangeChange();
202 }
203
204 // a bit of sanity checks on the interleaving, save it for here to
205 // ensure that the system pointer is initialised
206 if (range.interleaved()) {
207 if (channels != range.stripes())
208 fatal("%s has %d interleaved address stripes but %d channel(s)\n",
209 name(), range.stripes(), channels);
210
211 if (addrMapping == Enums::RoRaBaChCo) {
212 if (rowBufferSize != range.granularity()) {
213 fatal("Channel interleaving of %s doesn't match RoRaBaChCo "
214 "address map\n", name());
215 }
216 } else if (addrMapping == Enums::RoRaBaCoCh ||
217 addrMapping == Enums::RoCoRaBaCh) {
218 // for the interleavings with channel bits in the bottom,
219 // if the system uses a channel striping granularity that
220 // is larger than the DRAM burst size, then map the
221 // sequential accesses within a stripe to a number of
222 // columns in the DRAM, effectively placing some of the
223 // lower-order column bits as the least-significant bits
224 // of the address (above the ones denoting the burst size)
225 assert(columnsPerStripe >= 1);
226
227 // channel striping has to be done at a granularity that
228 // is equal or larger to a cache line
229 if (system()->cacheLineSize() > range.granularity()) {
230 fatal("Channel interleaving of %s must be at least as large "
231 "as the cache line size\n", name());
232 }
233
234 // ...and equal or smaller than the row-buffer size
235 if (rowBufferSize < range.granularity()) {
236 fatal("Channel interleaving of %s must be at most as large "
237 "as the row-buffer size\n", name());
238 }
239 // this is essentially the check above, so just to be sure
240 assert(columnsPerStripe <= columnsPerRowBuffer);
241 }
242 }
242}
243
244void
245DRAMCtrl::startup()
246{
247 // remember the memory system mode of operation
248 isTimingMode = system()->isTimingMode();
249

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244
245void
246DRAMCtrl::startup()
247{
248 // remember the memory system mode of operation
249 isTimingMode = system()->isTimingMode();
250

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