dram_ctrl.cc (10618:bb665366cc00) dram_ctrl.cc (10619:6dd27a0e0d23)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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52#include "mem/dram_ctrl.hh"
53#include "sim/system.hh"
54
55using namespace std;
56using namespace Data;
57
58DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
59 AbstractMemory(p),
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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52#include "mem/dram_ctrl.hh"
53#include "sim/system.hh"
54
55using namespace std;
56using namespace Data;
57
58DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
59 AbstractMemory(p),
60 port(name() + ".port", *this),
60 port(name() + ".port", *this), isTimingMode(false),
61 retryRdReq(false), retryWrReq(false),
62 busState(READ),
63 nextReqEvent(this), respondEvent(this),
64 drainManager(NULL),
65 deviceSize(p->device_size),
66 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
67 deviceRowBufferSize(p->device_rowbuffer_size),
68 devicesPerRank(p->devices_per_rank),

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234 } else {
235 port.sendRangeChange();
236 }
237}
238
239void
240DRAMCtrl::startup()
241{
61 retryRdReq(false), retryWrReq(false),
62 busState(READ),
63 nextReqEvent(this), respondEvent(this),
64 drainManager(NULL),
65 deviceSize(p->device_size),
66 deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
67 deviceRowBufferSize(p->device_rowbuffer_size),
68 devicesPerRank(p->devices_per_rank),

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234 } else {
235 port.sendRangeChange();
236 }
237}
238
239void
240DRAMCtrl::startup()
241{
242 // timestamp offset should be in clock cycles for DRAMPower
243 timeStampOffset = divCeil(curTick(), tCK);
242 // remember the memory system mode of operation
243 isTimingMode = system()->isTimingMode();
244
244
245 // update the start tick for the precharge accounting to the
246 // current tick
247 for (auto r : ranks) {
248 r->startup(curTick() + tREFI - tRP);
249 }
245 if (isTimingMode) {
246 // timestamp offset should be in clock cycles for DRAMPower
247 timeStampOffset = divCeil(curTick(), tCK);
250
248
251 // shift the bus busy time sufficiently far ahead that we never
252 // have to worry about negative values when computing the time for
253 // the next request, this will add an insignificant bubble at the
254 // start of simulation
255 busBusyUntil = curTick() + tRP + tRCD + tCL;
249 // update the start tick for the precharge accounting to the
250 // current tick
251 for (auto r : ranks) {
252 r->startup(curTick() + tREFI - tRP);
253 }
254
255 // shift the bus busy time sufficiently far ahead that we never
256 // have to worry about negative values when computing the time for
257 // the next request, this will add an insignificant bubble at the
258 // start of simulation
259 busBusyUntil = curTick() + tRP + tRCD + tCL;
260 }
256}
257
258Tick
259DRAMCtrl::recvAtomic(PacketPtr pkt)
260{
261 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
262
263 // do the actual memory access and turn the packet into a response

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1550 pwrStateTick = curTick();
1551
1552 // kick off the refresh, and give ourselves enough time to
1553 // precharge
1554 schedule(refreshEvent, ref_tick);
1555}
1556
1557void
261}
262
263Tick
264DRAMCtrl::recvAtomic(PacketPtr pkt)
265{
266 DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr());
267
268 // do the actual memory access and turn the packet into a response

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1555 pwrStateTick = curTick();
1556
1557 // kick off the refresh, and give ourselves enough time to
1558 // precharge
1559 schedule(refreshEvent, ref_tick);
1560}
1561
1562void
1563DRAMCtrl::Rank::suspend()
1564{
1565 deschedule(refreshEvent);
1566}
1567
1568void
1558DRAMCtrl::Rank::checkDrainDone()
1559{
1560 // if this rank was waiting to drain it is now able to proceed to
1561 // precharge
1562 if (refreshState == REF_DRAIN) {
1563 DPRINTF(DRAM, "Refresh drain done, now precharging\n");
1564
1565 refreshState = REF_PRE;

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2192
2193 if (count)
2194 setDrainState(Drainable::Draining);
2195 else
2196 setDrainState(Drainable::Drained);
2197 return count;
2198}
2199
1569DRAMCtrl::Rank::checkDrainDone()
1570{
1571 // if this rank was waiting to drain it is now able to proceed to
1572 // precharge
1573 if (refreshState == REF_DRAIN) {
1574 DPRINTF(DRAM, "Refresh drain done, now precharging\n");
1575
1576 refreshState = REF_PRE;

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2203
2204 if (count)
2205 setDrainState(Drainable::Draining);
2206 else
2207 setDrainState(Drainable::Drained);
2208 return count;
2209}
2210
2211void
2212DRAMCtrl::drainResume()
2213{
2214 if (!isTimingMode && system()->isTimingMode()) {
2215 // if we switched to timing mode, kick things into action,
2216 // and behave as if we restored from a checkpoint
2217 startup();
2218 } else if (isTimingMode && !system()->isTimingMode()) {
2219 // if we switch from timing mode, stop the refresh events to
2220 // not cause issues with KVM
2221 for (auto r : ranks) {
2222 r->suspend();
2223 }
2224 }
2225
2226 // update the mode
2227 isTimingMode = system()->isTimingMode();
2228}
2229
2200DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
2201 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
2202 memory(_memory)
2203{ }
2204
2205AddrRangeList
2206DRAMCtrl::MemoryPort::getAddrRanges() const
2207{

--- 38 unchanged lines hidden --- 		2230DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory)
2231 : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this),
2232 memory(_memory)
2233{ }
2234
2235AddrRangeList
2236DRAMCtrl::MemoryPort::getAddrRanges() const
2237{

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