dram_ctrl.cc (10509:d5554f97c451) dram_ctrl.cc (10561:e1a853349529)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 101 unchanged lines hidden (view full) ---

110 actTicks[c].resize(activationLimit, 0);
111 }
112
113 // set the bank indices
114 for (int r = 0; r < ranksPerChannel; r++) {
115 for (int b = 0; b < banksPerRank; b++) {
116 banks[r][b].rank = r;
117 banks[r][b].bank = b;
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 101 unchanged lines hidden (view full) ---

110 actTicks[c].resize(activationLimit, 0);
111 }
112
113 // set the bank indices
114 for (int r = 0; r < ranksPerChannel; r++) {
115 for (int b = 0; b < banksPerRank; b++) {
116 banks[r][b].rank = r;
117 banks[r][b].bank = b;
118 // GDDR addressing of banks to BG is linear.
119 // Here we assume that all DRAM generations address bank groups as
120 // follows:
118 if (bankGroupArch) {
119 // Simply assign lower bits to bank group in order to
120 // rotate across bank groups as banks are incremented
121 // e.g. with 4 banks per bank group and 16 banks total:
122 // banks 0,4,8,12 are in bank group 0
123 // banks 1,5,9,13 are in bank group 1
124 // banks 2,6,10,14 are in bank group 2
125 // banks 3,7,11,15 are in bank group 3

--- 93 unchanged lines hidden (view full) ---

219 }
220 // tCCD_L should be greater than minimal, back-to-back burst delay
221 if (tCCD_L <= tBURST) {
222 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
223 "bank groups per rank (%d) is greater than 1\n",
224 tCCD_L, tBURST, bankGroupsPerRank);
225 }
226 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
121 if (bankGroupArch) {
122 // Simply assign lower bits to bank group in order to
123 // rotate across bank groups as banks are incremented
124 // e.g. with 4 banks per bank group and 16 banks total:
125 // banks 0,4,8,12 are in bank group 0
126 // banks 1,5,9,13 are in bank group 1
127 // banks 2,6,10,14 are in bank group 2
128 // banks 3,7,11,15 are in bank group 3

--- 93 unchanged lines hidden (view full) ---

222 }
223 // tCCD_L should be greater than minimal, back-to-back burst delay
224 if (tCCD_L <= tBURST) {
225 fatal("tCCD_L (%d) should be larger than tBURST (%d) when "
226 "bank groups per rank (%d) is greater than 1\n",
227 tCCD_L, tBURST, bankGroupsPerRank);
228 }
229 // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay
227 if (tRRD_L <= tRRD) {
230 // some datasheets might specify it equal to tRRD
231 if (tRRD_L < tRRD) {
228 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
229 "bank groups per rank (%d) is greater than 1\n",
230 tRRD_L, tRRD, bankGroupsPerRank);
231 }
232 }
233
234}
235

--- 1909 unchanged lines hidden --- 		232 fatal("tRRD_L (%d) should be larger than tRRD (%d) when "
233 "bank groups per rank (%d) is greater than 1\n",
234 tRRD_L, tRRD, bankGroupsPerRank);
235 }
236 }
237
238}
239

--- 1909 unchanged lines hidden ---